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A Biometric system is essentially a pattern recognition system that makes use of biometric traits to recognize individuals. Authentication systems built on only one biometric modality may not fulfill the requirements of demanding applications in terms of properties such as performance, acceptability and distinctiveness. Most of the unimodal biometrics systems have problems such as noise in collected...
This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patterns...
In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave-pipelining achieves high speed without the above limitations. Wave-pipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks...
In this paper a modified simple edge preserved denoising algorithm to remove salt and pepper noise in digital color images is presented. The algorithm has three steps: noisy pixel detection, replacement of noisy pixels, confirmation by comparing with a threshold. In additon a median filtering is added to improve the qualityof the image. The proposed algorithm prevents the smoothing of edges in the...
A Biometric system is essentially a pattern recognition system that makes use of biometric traits to recognize individuals. Authentication systems built on only one biometric modality may not fulfill the requirements of demanding applications in terms of properties such as performance, acceptability and distinctiveness. Most of the unimodal biometrics systems have problems such as noise in collected...
This paper introduces a novel technique to detect faces in real-time with very high detection rate. It is essentially a feature-based approach, in which a classifier is trained for Haar-like rectangular features selected by AdaBoost algorithm and efficient representation method histogram equalization is used for varying illumination in the image. The face detection system generates an integral image...
In this paper, novel ideas have been proposed for designing and implementing the pipelined MB-OFDM UWB transmitter Digital Backend Modules on FPGA for a data rate of 200 Mbps. The various digital backend modules are scrambler, convolutional encoder, puncturer, interleaver, QPSK mapping, and OFDM. The most critical block is the OFDM block because it consists of 128 point IFFT, that to work at a speed...
This paper presents a method of encryption that enhances the security of vital data against brute force attack. The method is based on dual key encryption in which two different keys encrypt the data simultaneously, one being the regular key and the other being the time of key entry. The encryption process uses conventional encryption methods with some modifications to increase the security but the...
In this paper, a novel scheme is proposed for the implementation of FPGA based digital systems using asynchronous pipelining technique. To control the asynchronous data flow between stages, an intelligent controller is designed which decides the delay of each stage depending upon the magnitude of the input data (Data Dependent Delay). The intelligent controller has been designed using NIOS II soft...
Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower power consumption, design reuse without compromise in speed. In this paper, a new technique i.e., "SOPC based Asynchronous Pipelining Technique" (SOPC - System On Programmable Chip) is used for designing and implementing FPGA based Low- Power VLSI Systems. In this approach, the...
A novel methodology for testing all digital systems fused onto the FPGA has been developed in this paper. This methodology does not require any hook-up and input/output (I/O) interfacing card. This methodology uses the NIOS processor core to configure system onto the FPGA. HDL code of the digital system along with NIOS core is downloaded onto the FPGA. The NIOS processor can be programmed, to supply...
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