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We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed...
We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each...
To achieve ultimate super chip integration, we have developed a three-dimensional integration technology called super-smart-stack technology using a self-assembly technique. The chip alignment accuracy of within 1mum is obtained by the self-assembly technique. We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS)...
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