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This paper describes the applications of cluster ion implantation for beyond 45 nm node novel devices. A) Metal/high-k MOSFET: a flash lamp annealing (FLA) has advantage of dopant diffusion-less characteristics, but it requires suitable angle control for optimum gate overlap length. Cluster boron implantation with tilted SDE implantation for p-FETs has superiority over monomer boron implantation with...
This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron...
Comparisons between B, Ge+B and B18H22 implantations for pSDE were made. With Flash only the localized individual Xe-lamps signature was clearly detected by PLi and Rs measurements. Adding a spike first RTA anneal dramatically improved the global and local micro uniformity variation by 2-3x with either a 1000degC or 900degC spike 1st anneal. The highest quality B junctions were achieved with B18H22...
In this paper, the authors propose novel thin-body SOI FETs with NiSi-cladding. NiSi-cladding is fabricated after the formation of the sacrificing Si layer, and hence the Si consumption in SOI layer is minimized. It is found that NiSi cladding provides compressive strain in pFETs, which causes one order of magnitude decrease in pFET's off-current. In addition to the effect of NiSi-cladding, the influence...
A novel technique for the control of nitrogen (N) and oxygen (O) concentrations in the metal/high-k gate stacks is proposed. By inserting a reactive metal (Ti) layer remote from work function metal and high-k insulator, N and O concentration is easily decreased. This technique effectively suppresses the EOT increase after high-temperature annealing. Moreover, improved electron mobility and decreased...
We have realized a 0.9nm-EOT TaSix/HfSiON gate stack that exhibits the high electron mobility of 264 cm2/Vs @ 0.8MV/cm (86% of thermal SiO2), even after spike annealing at 1000degC. This was achieved by using thermally-stable HfSiON gate dielectrics with plasma nitridation, in which interfacial layer growth due to recoiled oxygen had been successfully suppressed
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