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We briefly discuss the evolution of Non-Volatile Memory (NVM) technology in term of macro-trends and their implications for modeling activities in an industrial R&D environment. Some examples of difficult modeling issues for different NVM techologies are mentioned, and finally both present needs and future challanges are critically reviewed.
This paper proposes a novel symbol timing estimation technique for multiband orthogonal frequency division multiplexing (MB-OFDM) based ultra wideband system. The symbol timing is estimated in two steps namely, coarse synchronization and fine synchronization. The coarse synchronization is obtained using the correlation between adjacent symbols. A new algorithm is proposed using maximum likelihood...
The feasibility of mesoporous silica as support to NiMo catalysts for hydrotreating of gas oil derived from Athabasca bitumen was tested in a trickle bed reactor at industrial conditions. High quality two dimensional (2D) hexagonal SBA-15 and three dimensional (3D) cubic KIT-6 supports were prepared by sol–gel method. The supports and catalysts were characterized by different characterization techniques...
Reduction of electrical parameter variation is essential to achieve high yield and reliability in semiconductor devices. However, variation depends on a large number of process factors, which are often interdependent. In this work, well-calibrated Technology Computer-Aided-Design process and device simulations were performed in a designed experiment to develop an efficient, surrogate response surface...
A new Technology CAD (TCAD) methodology has been applied to accurately extract cell-cell interference. The new method uses a "DeltaVt ratio" model instead of the conventional "capacitance ratio" model. The new method will be introduced and validated by recent experimental data. The predictions of the cell-cell interference on sub-40 nm floating gate (FG) cells and charge trapped...
Threshold voltage and drive current for a cylindrical MOSFET have been rigorously derived for the first time. An approximate expression for these quantities is presented for the purpose of analytical calculations. The model has been verified against TCAD simulations. The characteristics of a recessed gate MOSFET is analysed using these models.
The programming/erasing transient behavior of the NAND-type nanodot flash cell has been studied for the first time. By using an equivalent circuit model, the transient current through each layer in the dielectric stack can be monitored during the pulse programming/erasing. It is found that the oxide charging current leads the tunneling current during programming, and the charge built up at the storage...
Tapeout has evolved from an event marking the end of design to a process where substantial compute resources are used to apply reticle enhancement techniques to product design prior to mask manufacturing. A tapeout execution system (TES) has been developed that provides centralized visibility, controllability and automated execution to the entire tapeout process. TES provides a system for identifying...
As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics. Some of the challenges are common between these technologies while some are unique. New materials and cell structures are being introduced to address some of these issues and provide further scaling opportunities.
In the era of nanotechnology, variability detection and control in the manufacturing process is vital in delivering products at high yields and at optimal cost. At Intel, DFM techniques are utilized to combat variability at all stages of product delivery-design, tape-out, mask generation, fab processing and assembly. Statistical process control (SPC), advanced process control (APC) and fault detection...
The small-signal conductance technique was extended to extract asymmetric source/drain parasitic resistances. It was also applied in order to analyze the tWR delay of DRAM cell transistors in production and to develop a non-planar cell transistor such as recessed access device (RAD) for low-power DRAM cells. Factors limiting the drive current for planar and non-planar access transistors in the low-power...
Thermally stable TiN and TaN-TiN laminate metal gates for PFETs are demonstrated using a conventional CMOS process flow with SiON gate dielectric. TaN-TiN laminate gates show enhanced drives (ID), higher transconductance (GM), higher mobility (mu EFF , and reduced off current (IOFF) characteristics compared to TiN gates. The optimum thickness of TaN in the laminate stack is discussed. The as-deposited...
After a three year development and integration effort, Intel has successfully implemented a next generation MES system (referred to as MES300 henceforth this paper) in its state-of-the-art Technology Development fab DID, Oregon. MES300 provides integration of all MES functionality in an extensible framework based architecture, thereby enabling delivery of an active, fab event driven suite of capabilities...
With the rapidly advancing semiconductor technology and competitive business conditions, it is very crucial to maintain high operation efficiency and maximize the key product throughput to supply market in a timely manner. Dynamic WIP (work in process) dispatching is a new technology to efficiently dispatch semiconductor manufacturing materials to desired tools for lot process promptly in response...
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