The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Summary form only. A biography is presented of Iddo Hadar (Chief Technology Officer, Chief Marketing Officer and Strategy Officer, Foundation engineering Group, Applied Materials, Inc.).
In the era of nanotechnology, variability detection and control in the manufacturing process is vital in delivering products at high yields and at optimal cost. At Intel, DFM techniques are utilized to combat variability at all stages of product delivery-design, tape-out, mask generation, fab processing and assembly. Statistical process control (SPC), advanced process control (APC) and fault detection...
The availability of a precise physical description of the imaging system that was used to expose an OPC calibration tests pattern is now possible. This data is available from scanner manufacturers of the tool as built and also by scanner self-metrology in the Fab at any time. This information reduces significant uncertainty when regressing a model used for OPC and allows the creation of more accurate...
IBM has taken several steps in developing an analysis and optimization framework for VLSI layouts. We have deployed automated tools to reduce the sensitivity of designs to certain defect mechanisms in the manufacturing process. We see a clear need for expanding and refining tMs work and then integrating it with rigorous characterization of manufacturing processes and at the same time developing and...
The complexity of modern manufacturing processes has sharply increased the number of steps affecting device and circuit performance. We discuss a number of critical steps, their control methodology and how to minimize the time to detect. Product test results and data-mining are used to identify critical steps and to determine which inline signals require most attention. The last section is devoted...
In this work, a novel SPC monitor of RTP temperature was developed where measurements are made directly on product. This technique significantly reduces test wafer costs while allowing real-time determination of functionality directly on the area of interest. The technique is useful over the entire operational range of the tool temperatures. However, in this latter cases reusable test wafers are needed...
For state of the art microelectronic technologies, reliability is a major challenge. Mechanical stress induced by the process steps is often at the origin of yield losses. Degradations of electronic devices are usually correlated to the presence of defects such as dislocations, cracks or delaminations. Usual methods for mechanical stress measurement generally require off-line measurements and are...
The aggressive shrinking of design rules with the increasing requirement to reduce costs of running a 300 mm Fab are pushing equipment particle performance to lower defectivity counts and tighter control. The rapid qualification of process equipment and the identification of excursions on monitor wafers before the product is committed is an important metric of a Fab strategy to minimize the product...
A test structure specifically designed to allow in-line detection of missing spacer is introduced. Missing spacer is too small to be physically detected with any current inspection tool and therefore its existence must be flagged using voltage contrast for detection with an e-beam inspection system. How this structure and methodology were used to address this defect during the ramp of a recent technology...
Advanced bright field inspection tools available today applied on development wafer may often result in 100 k to 1 M defects per wafer. Such defect data consist of systematic and random defects that may be yield limiting or may be just cosmetic issue with low probability of yield impact. It is also difficult to identify systematic defects from random defects by using traditional defect classification...
The article describes the wafer yield loss due to wafer backside defect. The backside defect pattern will transfer to the next wafer surface during the following clean process and cause the process defect issue. These defects will impact the yield. Real root cause finding let prevent action work well.
As IC technology advances result in progressively smaller device dimensions, understanding and characterizing the impact of process variations on wafer surface conditions and identifying potential surface damage becomes critical. UV laser scattering technology enables full-wafer surface monitoring with sub-nm vertical resolution and high throughput. This technique has been shown to be sensitive to...
This paper describes an integrated methodology that combines short-flow test chips useful for exploring process-design systematic as well as random failure modes and an advanced inspection tool platform to characterize and monitor key Defects-of-Interest for accelerated defect-based yield learning at the 65 nm technology node. Utilization of a unique fast electrical testing scheme, rapid analysis...
Progressive mask defect (such as crystal growth, haze etc.) continues to threaten the industry (especially at 193 nm lithography) [1]. This drives the need for wafer fab mask inspection [2] which can be achieved via two methods. The first method is indirect, commonly known as image qualification[4], where a mask is being exposed followed by the inspection of the printed wafer to detect if there is...
To help address the need for manufacturing cycle time reduction, Intel has adopted an integrated approach that consists of three key components - targeting, near real-time scheduling, and dispatching - that work in conjunction to maximize fab efficiency. Combined with fully automated execution, this approach allows Intel to execute to a coordinated operational management philosophy at its fabrication...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.