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This paper presents a novel low voltage LDMOS structure with low on-resistance based on 0.13 μm CMOS technology. 8 V/9 V Nch LDMOS have only 0.3 μm gate length when the maximum gate operating voltage is 5 V, while the gate length of 5 V CMOS is 0.6 μm to avoid the short channel effect. The obtained specific on-resistance are 1.8 mΩmm2 (8 V Nch LDMOS) and 5.9 mΩmm2 (8 V Pch LDMOS) respectively. Furthermore...
In this paper, a fabrication method of suspended silicon microfluidic channels and various shapes of microstructures of desired thickness in (100)-Si wafers using single photolithography step is presented. The fabrication method uses wafer bonding with silicon nitride (Si3N4) as intermediate layer, local oxidation of silicon (LOCOS), and complementary metal oxide semiconductor (CMOS) process compatible...
In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and...
A semi-dynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow
A 0.25µm 2.5V CMOS analog front-end IC for an ADSL system is presented. The IC contains all analog functions including gain-controlled transmit and receive amplifiers, highly linear continuous-time low pass filtering including on-chip automatic tuning, 8.8Ms/s ADC and DAC as well as a crystal driver and a DAC-controlled VCO. The IC has been realized in a mixed-signal 0.25µm triple-well CMOS technology,...
This paper proposes a new plasma damage model that can explain and estimate the plasma damage in a CMOS LSI by taking into account the additional factor of pattern density. Reliability data presented in this paper shows that plasma damage to MOSFET gate oxide in a CMOS LSI cannot be fully explained by considering only antenna and aspect ratio theory. To verify the model on a CMOS LSI, a test pattern...
A 1- mu A-retention, 4-Mb SRAM with a thin-film-transistor (TFT) load cell, fabricated in a 0.5- mu m triple-poly-Si (first- and third-level W-polycide) double-Al CMOS technology is described. A 200-fA/b retention current is achieved. utilizing the PMOS-type TFT, in which the n/sup +/ diffusion area of the driver transistor acts as a gate electrode of the TFT. The RAM, which has a built-in voltage...
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