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We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
In this study, the field electron emission from the vertically well-aligned CNTs catalytically synthesized in liquid methanol was measured to determine the relation between the emission properties and their morphologies. Heavily doped n-type silicon (Si) wafers with a low resistivity less than 0.02 Ω cm were used as a substrate for the CNT growth. The morphology and fine structure of the grown CNTs...
Field emission characteristics of the carbon nanomaterials with different surface morphologies have been measured. They were catalytically grown in the organic liquid of 1-octanethiol (CH3(CH2)7SH) with using Co as a catalyst. A thick fibriform or a film-like structured carbon nanomaterial was grown by the control of the phisco-chemical states of Co catalyst. The thick fibriform materials indicated...
Fatigue tests of silicon stepped cantilevers fabricated from silicon on insulator (SOI) wafers were conducted under the bending mode to evaluate the effect of cyclic loading on fractures occurring in silicon and Si/SiO2 interfaces. The specimen in the quasi-static mode fractured at the stress concentration site on the silicon specimens. However, during the fatigue tests the cantilever broke after...
Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12??) for BE nFET devices to-date, consistent with simulations showing the need for ≪14??...
We have developed a high performance pMOSFET with ALD-TiN/HfO2 gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+poly-Si/SiO2 on (110) substrate (171 cm2/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO2 on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off...
We have developed a dual metal gate CMOS technology with HfSix for nMOS and Ru for pMOS on HfO2 gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to Tinv of 1.7 nm and symmetrical low Vt equivalent to poly-Si/SiO2. As a result, high drive currents of 780 muA/mum and 265 muA/mum at Ioff = 1 nA/mum are achieved for Vdd...
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