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Multi-context reconfigurable arrays provide the ability for fast dynamic reconfiguration once the configurations have been stored into the architecture's context memory. Besides switching the context of the entire array it is also possible to reconfigure contexts from outside the array, which we call external reconfiguration. If supported by the architecture, this reconfiguration, as well as switching...
In the last years, aside from fine-grained reconfigurable architectures such as FPGAs, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional FPGAs in terms of area and...
In dynamically reconfigurable processors, different contexts as well as different data paths within one context usually vary in their execution time. Voltage scaling offers the ability to utilize this variation to reduce power consumption. In this paper, we propose a dual-VDD dynamically reconfigurable processor architecture which utilizes the varying execution time to reduce dynamic power consumption...
It is well known that the area efficiency of a digital circuit can be improved by reconfiguration due to the reuse of resources. In this paper, we show that this benefit can be achieved for a wide range of applications if the reconfiguration can take place within each clock cycle, and we quantify the benefit by area estimations from a synthesizable architecture model. Although reconfiguration typically...
Traditionally, FPGAs are deployed because of their flexibility to change the application over time. Newly developed architectures can be reconfigured within one clock cycle so that components of a device can be re-used within a single application. The reconfiguration keeping pace with the execution yields an additional degree of freedom that constitutes a new principle of reconfiguration. This principle...
There is a growing number of reconfigurable architectures that combine the advantages of a hardwired implementation (performance, power consumption) with the advantages of a software solution (flexibility, time to market). Today, there are devices on the market that can be dynamically reconfigured at run-time within one clock cycle. But the benefits of these architectures can only be utilized if applications...
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