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We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise...
With shrinking feature sizes of manufacturing processes, the occurrence of systematic defects is expected to increase. In this paper, we present techniques for identifying potential systematic defect candidates from design-for-manufacturing (DFM) layout guidelines. DFM guidelines are tightened to find layout locations as potential sites for systematic defects, affected transistors are identified at...
An n-detection test set contains n different tests for each target fault. The value of n is typically determined based on test set size constraints, and certain values have become standard. In this work we investigate appropriate values for n by considering the saturation of the n-detection test generation process. As n is increased, eventually the rate of increase in test set quality starts dropping...
The use of multiple scan chains was shown to improve the coverage of transition faults achieved by skewed-load tests. For broadside tests, the number of scan chains does not affect the transition fault coverage. We describe an enhanced broadside configuration under which increasing the number of scan chains helps increase the fault coverage. In the enhanced configuration, the first flip-flop of a...
We describe a diagnostic test generation procedure that targets the equivalence classes of the test set as it is being generated, instead of considering one fault pair at a time (an equivalence class contains faults that are indistinguished by the test set). When an equivalence class is targeted, all the fault pairs in the equivalence class are targeted simultaneously. This reduces the number of test...
Functional test sequences were shown to detect defects that are not detected by structural tests. They also help in avoiding overtesting. However, fault simulation to compute the stuck-at fault coverage of functional test sequences can be time consuming especially in applications where a large number of test sequences need to be evaluated and compared. To obtain fast yet accurate estimates of the...
We describe a method for on-line testing of delay faults based on the comparison of output responses of identical circuits. The method allows one of the circuits to participate in useful computations during the testing process, while the other circuit must be idle. We refer to this method as semi-concurrent on-line testing. While unknown input vectors are applied to the circuit that participates in...
Z-diagnosis was proposed for speeding up diagnostic fault simulation by identifying in an efficient manner fault pairs that are guaranteed to be distinguished by a fault detection test set. Z-diagnosis is based on z-sets, which capture information about the outputs to which fault effects may be propagated. We introduce a dual concept of a-diagnosis that is based on a-sets, which capture fault activation...
We describe a diagnostic test generation procedure that deals with the large numbers of target fault pairs by considering subsets of faults. Each subset of faults is targeted separately during diagnostic test generation, and fault pairs are defined only out of the faults included in a subset. With M subsets of size K, the number of fault pairs considered is at most MK(K-1)/2 instead of N(N-1)/2 for...
Autoscan is a design-for-testability approach proposed earlier that uses scan chains without external scan inputs or outputs in order to reduce the test application time and test data volume of scan. We describe three improvements to the basic autoscan design-for-testability approach based on the following observation. Under autoscan, due to the elimination of external scan inputs, the first flip-flop...
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values that should not be assigned to inputs in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation...
Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift test method has the advantage that it provides higher fault coverage at reduced test generation time and test pattern counts. However a concern expressed often in the literature is the potential over testing or yield loss caused...
Open defects in CMOS circuits require two-pattern tests for detection. Traditionally, the only two-pattern tests included in manufacturing test are those targeting transition delay faults. Such tests, however, do not provide complete coverage of all the open defects. In this paper we propose the use of a unified test set that detects all inline resistance faults which model interconnect open defects...
We show that the functionality of scan chain inputs sometimes exists in a circuit as part of its functional operation, and can be exhibited by applying specific primary input vectors. By relying on such functionality it is possible to hide scan chains as part of a solution that addresses security. It is also possible to reduce the number of external scan chain inputs that need to be added to the circuit...
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal operation conditions. However, fault simulation and test generation for the existing fault models become significantly more complex due to the need...
In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved...
Generation of n-detection test sets is typically done for a single fault model. In this work we investigate the generation of n-detection test sets by pairing each fault of a target fault model with n faults of a different fault model. Tests are generated such that they detect both faults of a pair. To facilitate test generation, we ensure that the faults included in a single pair have overlapping...
The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously...
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application time for stuck-at faults. We show that similar advantages exist when considering transition faults. We first show that a test sequence under the transparent-scan approach can imitate the application of broadside tests for...
Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use...
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