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In this paper, a CMOS tail-filtering VCO using Helium-3 ion irradiated Q-enhanced inductors is presented. The prototype of this VCO is implemented in a standard 65-nm CMOS process. An improvement of approximately 2.5dB in FoM is achieved after the Helium-3 ion irradiation because of the inductor quality factor improvement. The VCO achieves a phase noise of −116.4dBc/Hz at 1MHz offset while only consuming...
In this paper, a 60 GHz CMOS on-chip dipole antenna with helium-3 ion irradiated silicon substrate is designed using knowledge of electromagnetic simulation modeling. Rectangular region with 500 um × 1000 um around the dipole is irradiated by helium-3 ion and conductivity is reduced to 0.01 S/m (1 k Ohm cm). The width of dipole section is wide for broad bandwidth and reduction of conductor loss. There...
Helium-3 ion irradiation technique is proposed to improve silicon substrate noise isolation by creating a local semi-insulated region with a resistivity over 1kΩ-cm in low-resistive silicon substrate. Noise isolation is improved about 10dB at 2GHz after helium-3 ion irradiation in a 180-nm CMOS process. A 90% noise reduction has been achieved in the measurement results for test structures with guard...
A helium-3 ion bombardment technique is proposed to realize high-$Q$ inductors by creating locally semi-insulating substrate areas. A dose of $1.0\times 10^{13}$ cm$^{-2}$ helium-3 increases a Si substrate resistivity from 4 $\Omega \cdot $ cm to above 1 $\text{k}\Omega \cdot $ cm, which improves the quality factor of a 2-nH inductor with a 140-$\mu \text{m}$ diameter by 38% ($Q=16.3$ ...
A 60-GHz CMOS on-chip dipole antenna with efficiency-enhancement technique is presented. A helium-3 ion irradiation process is used to reduce the substrate losses of the on-chip antenna. The radiation efficiency of the antenna is doubled using the ion implantation technique. The antenna is fabricated in a 65-nm CMOS technology with a core area of 0.48 mm2. The on-chip antenna achieves a peak gain...
A 60-GHz CMOS transmitter with on-chip antenna for high-speed short-range wireless interconnection is presented. The radiation efficiency of the on-chip antenna is doubled using substrate loss improvement techniques. The transmitter fabricated in a 65-nm CMOS process achieves over 5Gb/s data rate with an EVM performance of −12 dB for BPSK modulation. The whole transmitter consumes 17 mW from a 1.2-V...
A novel helium-3 ion bombardment technique is proposed for creating locally semi-insulating substrate areas. A helium-3 dose of only 1.5×1013cm−2 increases a Si substrate resistivity from 6Ω-cm to 1.5kΩ-cm, which improves the quality factor of a 2-nH inductor with a 140µm-diameter by 38% (Q=16.3). An aluminum mask is used for covering active areas, and at most 15-µm distance from the mask edge is...
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