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In this paper a new VCO-based MASH delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization error...
Noise coupling and time interleaving are effective methods for expanding the bandwidth of the low-power wideband delta-sigma modulators. In this paper, a discrete-time ΔΣ modulator topology with these two technologies, combined with shifted loop delays, is proposed. Noise coupling and time interleaving between the two channels enhance the effective order of the noise shaping function. Shifting the...
A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is high due to the reduced number of clock phases and switches connected to each capacitor. Also, this scheme decreases the filter nonlinearity. Verified by simulations, the noise analysis of the filter shows superior performance compared to active SC filters. These features, and a wide frequency tuning range,...
A novel sequential inter-stage correlated double sampling technique has been proposed. This technique provides considerable enhancement in the effective accuracy of a switched-capacitor architecture. Superior accuracy and thermal noise performance is achieved compared to the conventional correlated double sampling technique. The proposed approach provides higher input signal bandwidth by reducing...
A counting analog-to-digital converter (ADC) is proposed which achieves a high sampling rate by performing the conversion in several (N) steps. In terms of the effective number of bits (ENOB) of the ADC, the conversion time of the ADC is approximately N.2ENOB/N clock periods, which is much shorter than for traditional counting ADCs (2ENOB clock periods). This is achieved by using novel methods of...
This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using...
A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. Further power consumption reduction is achieved by using sense-amplifier-based slicer and pass-gate multiplexer...
This paper presents an improved PMOS-based active inductor circuit suitable for output driver in wireline link transmitters. Wider tuning range and higher inductive impedance in the desired bandwidth with respect to a previous reported topology is achieved using a varactor in the active inductor architecture and modifying the feedback resistor. Using the proposed active inductor, a prototype output...
In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5-bit resolution,...
In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise....
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