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This paper brings a comparison of the traps identified in triple-gate FinFETS and Gate-All-Around (GAA) nanowire (NW) MOSFETs built with the same technological process. Traps have been identified using low frequency noise (LFN) spectroscopy, giving information on which process steps may be improved in order to build better devices.
This paper studies for the first time the low temperature characteristics of strained SOI FinFETs submitted to proton irradiation. Both types of transistors, nMOS and pMOS, were analyzed from room temperature down to 100K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA and the intrinsic gain voltage (AV). The effects of strain techniques are also studied. The...
The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to...
The impact of cryogenic temperature operation on the short channel effects and analog performances was analysed on strained and unstrained p-channel SOI FinFETs. The main electrical parameters extracted from the saturation mode of operation are investigated and compared to those found at room temperature. Low frequency noise measurements at 10 K operation show that the carrier number fluctuations...
In this paper, the floating body effect (FBE) is experimentally investigated on triple gate n-channel Bulk FinFETs for 1T-FBRAM (1 transistor Floating Body Dynamic Random Access Memory) application. A difference between the Direct Current (DC) and the Alternating Current (AC) measurements corresponding with the real memory operation is shown. The large hysteresis under DC measurement related to floating...
DC and low frequency noise measurements on strained and unstrained n-channel FinFET transistors processed on silicon on insulator (SOI) substrates were performed at 10 K in order to evaluate the device performances and study the low frequency noise mechanisms. The main electrical parameters are investigated and compared to those found at room temperature. The low frequency noise analysis shows that...
This paper aims at the studying the low frequency noise from 100 K up to room temperature in n- and p-channel triple-gate FinFET transistors with 25 nm fin-width, 65 nm fin-height, a high-k dielectric / metal gate stack, strained and unstrained substrates. These investigations allow evaluating the quality of the gate oxide interface, to identify defects in the silicon film and to make a correlation...
Pulsed laser-induced current transient experiments are used to understand the mechanisms of single-event effects in bulk and fully depleted silicon-on-insulator p-channel FinFETs. The drain current transients are significantly larger in the bulk FinFETs than in the SOI devices. Bulk FinFETs collected 270 times more charge than SOI FinFETs. 98% of the charge collected in the bulk FinFETs is generated...
This paper presents, for the first time, the operation of triple-gate FinFETs with HfO2 gate dielectric, TiN gate and undoped body at cryogenic temperatures. Emphasis for the most common analog figures of merit is given as the intrinsic gain (AV) and the unity gain frequency (fT)
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