The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)-magnetoresistive random-access memory (MRAM)-hybrid LUTs the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors...
This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO...
HfOx RRAM is a most promising candidate for next generation nonvolatile memory with highest endurance, speed till now but bipolar switching affects the selection of steering device, performance and applications. Bipolar and unipolar RRAMs have their advocators. Cell area of 4F2 and/or 3D stacking for high density applications is the determining factor of preferring unipolar device. High operation...
This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random access time is presented. Multi-level-cell (MLC) operation with 160ns write-verify operation is demonstrated.
This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations. The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control...
A 1-Kb HfO2 based RRAM for high speed nonvolatile memory application is proposed. With this chip, a high speed write characteristic in the RRAM cell can be achieved. The present circuit design includes a 1T1R RRAM (1 transistor/1 resistive memory) cell and a voltage write circuit, which limit the current through the memory cell. The random write time at VDD = 3.3V is as fast as 5 ns in the RRAM, which...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.