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Networks-on-Chip (NoCs) are the backbone of communications in MPSoCs and future Many-Cores. The approaching thousand cores technology, together with the dark silicon era, put energy-efficiency on top of the challenges for future NoC-based multicore chips, where NoCs significantly contribute to the total chip power. This paper explores the use of circuit-switched (CS) NoCs as a low complexity energy-efficient...
Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex...
The four papers in this session present novel methodologies covering different aspects of system design. The first paper proposes a decentralized system-level security approach for task isolation on heterogeneous MPSoCs. A first prototype of the isolation unit is presented and realized in VHDL. The second paper focuses on low power design methods for system design based on lightweight dataflow programming...
The mapping process of high performance embedded applications to today's multiprocessor system on chip devices suffers from a complex tool chain and programming process. The problem here is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently...
This paper introduces a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed. The latter parameter is normally not known at design time. This leads to the development of more general purpose processors which are capable to handle the data to be processed in any...
While advances in processor architecture continues to increase hardware parallelism, parallel software creation is hard. There is an increasing need for tools and methodologies to narrow the entry gap for non-experts in parallel software development as well as to streamline the work for experts. This paper presents the methodology and algorithms for the creation of parallel software written in Scilab...
The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides...
Ad-hoc and dynamic adaptation to the requirements of an application enables to increase the energy efficiency of a processor. This method is especially for novel heterogeneous multicore systems of high interest since the various cores can be adapted individually. For this purpose, the current status of the system has to be monitored on the chip. Parameters of interest are the number of communications...
This paper presents a novel approach for a memory, which supports the flexibility of an FPGA-based dynamic reconfigurable System-on-Chip consisting of heterogeneous data processing nodes. The memory is accessible via the Network-on-Chip (NoC) and provides a dynamic mapping of address space for the different clients within the network. Different data transfer modes support especially the image processing...
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