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The electrical characteristics of Ti/p-SiGe contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. TiN was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/p-SiGe contact resistivity (ρc) increases, but its Schottky barrier height (SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using TiN/p-SiGe as a control sample,...
In this work, new halo profile engineering is proposed to suppress the threshold voltage variation (σVt) caused by discrete random dopant fluctuation (RDF). An in-house 3D atomistic numerical simulation tool is utilized to assess nMOSFETs σVt caused by RDF for a HK/MG process. The results show that σVt can be effectively suppressed by 10% by optimizing rotation and tilt angles of the halo implant.
The impact of aluminum (Al) implantation into TiN/HfO2/ SiO2 on the effective work function is investigated. Al implanted through poly-Si cannot attain sufficient flatband voltage (VFB) shift unless at higher implantation energy. Al implanted through TiN at 1.2 keV with a dose of 5 × 1015 cm-2 raised the VFB to about 250 mV compared with a nonimplanted gate stack. Moreover, the VFB shift can be up...
We present a novel calibration methodology that (i) integrates dopant diffusion, mechanical strain and bandgap narrowing for accurate device short channel effect modeling and (ii) deploys stress dependent mobility model for robust device performance projection especially on effective drive current (Ideff). Good agreement is obtained between the model calibration and experimental measurements over...
We present an in-house tool to simulate random dopant fluctuation effects on nano-scale devices with nonuniform channel doping profiles. A novel dopant discretization scheme using Poisson statistics that can achieve self-consistent median parametric values (e.g. average channel concentration) with deterministic device simulations was introduced. This capability was deployed to study the variability...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only...
We demonstrate for the first time the CMOS integration combining inserted metal with FUSI using a novel process flow. The proposed flow allows for a flexible gate electrode and dielectric choice for island PMOSFETS, without adding excessive process complexity or additional masks. It is considered as a promising alternative for dual metal integration for 45 nm bulk CMOS technology and beyond.
We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using...
We report record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report presented in A. Lauwers et al. (2005). First, we have improved the (unstrained) devices Idsat to be 560/245muA/mum for nMOS/pMOS at an Ioff = 20pA/mum and V...
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