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6T SRAMs have been the embedded memory of choice for modern microproces sors due to their logic compatibility, high speed, and refresh-free operation. The relatively large cell size and conflicting requirements for read and write at low operating voltages make aggressive scaling of 6T SRAMs challenging in sub 22nm. Recently, 1T1C embedded DRAMs (eDRAMs) have replaced SRAMs in several server applications...
This paper presents an 8 × 8 DRAM array fabricated using an aerosol jet printer to demonstrate the feasibility of gain-cell DRAMs in a p-type-only organic thin film transistor (OTFT) technology. This printing method can accommodate functional inks with a variety of viscosities and has a patterning precision of 10 μm. The underlying design philosophy was to implement a general purpose memory array...
Feasibility of STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) as next generation non-volatile memory has been tested for the replacement of DRAM and NOR Flash. For competition with DRAM, STT-MRAM unit cell size should be reduced to 6 ~ 8F2 and switching current density is required to be less than 1 MA/cm2. Here, we report that the cell characteristics of on-axis STT-MRAM with 6 ~ 8F...
A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL...
A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation...
Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node voltage monitor to overcome the data `1' write disturbance problem. An adaptive and die-to-die adjustable...
We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F2 (0.0036 μm2) feature size. From the 2D TCAD simulation of the SBE...
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided...
We present single event effect (SEE) and total ionizing dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer
The SiGe SD structure in peripheral PMOS area of DRAM was successfully integrated without any degradation of peripheral NMOS properties, which is the first approach to DRAM. The PMOS performance enhancement was found to be more than 40%. The authors suggest the SiGe SD structure as the key solution for the improvement of peripheral PMOS transistor properties in sub-50nm DRAM technology
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