The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper we show the strong influence of the composition of the Cu-Te alloy on the conductive-bridging RAM operation of Cu-Te/Al2O3/Si cells. The Cu filament generated during forming and set operations requires lower reset current for lower x in the CuxTe1-x layer. Optimum memory operation is determined for the range 0.5<;x<;0.7, which allows self-limited filament programming using 5μA...
We demonstrate a novel low-voltage biasing scheme on ultra-thin BOX (UTBOX) FDSOI floating body cells with Lg=55nm and tSi=20nm. By optimizing the front and back gate biasing to enhance the positive feedback loop, the required VDS can be reduced to 1.5V while retention times as high as 5s can still be achieved at 85°C. For the first time, we also show that the stringent endurance spec of 1016 cycles...
Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in the fin. The impact of the ground plane doping is investigated and finally the read-out scheme is also demonstrated on SOI FinFET devices.
This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved...
A comprehensive analysis of operational tall triple-gate MuGFET ring oscillators (ROs) is presented for the first time. Device geometries, process options and best inverter layout are discussed based on measured power and delay. A MOS model 11 based macro-model has been calibrated and correlated to hardware to enable a study on work-function tuning, conformal S/D extensions, strain engineering, raised...
Wireless applications require a low power technology that enables digital/analog/RF functions on the same chip. FinFET technology presents a competitive alternative to planar CMOS as it features good digital, analog and low-frequency noise performances. Also, very good matching performance is presented here for the first time. Moreover, FinFETs are shown to be attractive for low-power applications...
We report record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report presented in A. Lauwers et al. (2005). First, we have improved the (unstrained) devices Idsat to be 560/245muA/mum for nMOS/pMOS at an Ioff = 20pA/mum and V...
This report discusses a new and practical approach to implement low Vt bulk CMOS using Ni-based FUSI MOSFETs. On the nFET, we demonstrate for the first time that incorporating Yb by ion implantation can achieve similar reduction of effective work function (WF) compared to alloying making it a candidate for CMOS integration. We complement our previous work on WF modulation by Yb on NiSi/SiON with new...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.