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To achieve the automotive quality for semiconductor devices represented by “zero defect”, “PAT” is actively applied to outgoing test. “PAT” has been generally used on wafer level test. This time we expanded it to package level test and established the method to detect the characteristic variations and to screen out the outliers.
An enormous energy has been consumed in a semiconductor manufacturing factory. The energy consumption ratio for the use of manufacturing apparatus is approximately 60 percent in a semiconductor manufacturing factory, and the cost of energy is increasing in recent years. Therefore, We developed an energy saving controller for saving the energy of sub apparatus. We introduced the controller to the dry...
A new approach in FDC takes advantage of the full sensor trace for fault detection which allows engineers to uncover issues more thoroughly and accurately. The solution utilizes a reference model that intelligently adapts to process changes and requires minimal effort to set up. This greatly reduces the time required to deploy and virtually eliminates maintenance for an FDC system. The elimination...
We have developed the method for the monitoring of the condition of deposited film on the inner wall, which cause particles, in mass-production plasma etching equipment using a load impedance monitoring system. The results in this study demonstrate that the system can be used as a practical method for real-time and noninvasive monitoring of the inner wall condition of etching chambers.
ASML began collecting data off tools in fabs from ca 1986 for the purpose of diagnostics and troubleshooting. This continued on a manual basis through the 1980's and into the early 1990's when tools began to be connected to the fab network and to the internet. Following manual collection, networked data collection began to take shape and then remote collection began ca 1996. It was from then for the...
Threshold voltage (VTH) needs to be well controlled to determine the switching point of the transistors. However VTH variation was observed on high voltage transistor during development phase. Investigations show that the VTH variation was caused by phosphorus contamination from wafer backside. Various wet chemical cleaning methods were evaluated to understand the effectiveness for the phosphorus...
This paper describes the development and experimental results of a process control system. The system enabled adjusting film thickness and in-film dopant concentration at the same time on a batch LPCVD machine. By this, anyone could adjust process results easily and exactly in a short time.
In this article, we report about platform and architecture that real-time analysis of big data are possible, and structured IT infrastructure that they are optimally combined. We developed a distributed architecture which the data conversion and the abnormality determination are multi-blocked. Furthermore, by selecting a distributed storage DB, we succeeded in constructing IT infrastructure capable...
Engineers in the semiconductor domain are spending significant time searching for materials with certain properties, such as carrier mobility and bandgap values within certain ranges, or to keep informed about newly discovered materials with desirable properties. Since these searches are not anchored in keywords, the usual information retrieval tools are of limited utility. In this paper, we propose...
One of the key challenges in embedded memory solutions is yield degradation due to additional thermal budget in the process. In this work, we report STI HDP-CVD (Shallow Trench Isolation High-Density Plasma Chemical Vapor Deposition) process as a key contribution factor to yield degradation in embedded memory devices by causing higher degree of silicon dislocations. With optimized plasma sputter/deposition...
We report on the development and application of a brand-new contactless method based on eddy currents with a view to designing a generic apparatus for the characterization of some transport properties of a large range of semiconductors. The eddy current probe, constituted of a coil connected to a transmission line, interacts with the semiconductor wafer under inspection. The innovative approach of...
Improvement of Laterally Diffused Metal Oxide Semiconductor (LDMOS) energy capability, Unclamped inductive switching (UIS) is used to characterize ruggedness in terms of the maximum avalanche energy that device can handle prior to destructive breakdown. Maximum amount of UIS energy (EAS) sustained by device before failure is evaluated and have linear relationship with number of device finger and device-width...
Semiconductor wafer fabrication companies rely on continuously improving cycle time for agile manufacturing to maintain their competitive advantages. This study has illustrated how to apply data mining techniques, Back-Propagation Neural Networks (BPNN), to optimize the allocation of production resources in semiconductor wafer fabrication. The results in the empirical study have demonstrated significant...
The Factory Integration (FI) focus area of the IRDS is dedicated to ensure that the semiconductor manufacturing infrastructure contains the necessary components to produce increasingly complex and advanced integrated circuits and devices while extending the historical performance vs. cost trends expressed by Moore's Law. This requires taking full advantage of traditional measures (e.g., device feature...
Cycle-time improvement continue to be a big challenge to all fab production managers. In this paper, a dynamic cycle-time improvement plan through big data analytics is being discussed. After the implementation of this three-phase project, a ∼17% improvement in dynamic cycle-time is achieved without compromising fab utilization.
We constructed a system infrastructure capable of processing unstructured data, with the aim of practical application of the system for document data analysis in the manufacturing industry. Using past ISSM research paper data, papers were classified and verified. Using morphological analysis, the extracted parts of speech were used as feature quantities, and machine learning was executed. Since effective...
This paper introduces a systematic procedure of simultaneous allocation of multi-type resource. Two algorithms, QP2LP and a hueristic approach, were newly developed for fast computation required in make-to-order production. The proposed methods improved both the due-date satisfaction and tool utilization by 5% as the result of its performance evaluation of an actual wafer test process. The computational...
In chemical mechanical planarization (CMP) processes for semiconductor devices, more than one materials may appear as the polishing progresses. In the slurries for front end of line (FEOL) processes, removal rate (RR) enhancement for dielectric layer (silicon oxide, silicon nitride) and etching rate (ER) inhibition for plug materials (W and poly-Si) are needed. In this study, we designed a novel slurry...
Ultrapure water contains several kinds of contaminaminants. In particular, we paid much attention to particles and investigated particles adsorption onto Si wafer. We succeed in making a model through two experiments, that is, one is to study an impact of spin cleaning parameters on particle adsorption, and the other is to study that of such impurities as urea, hydrogen peroxide, and so on.
Laser scanning confocal fluorescent microscopy and the friction mode of Atomic Force Microscopy were adopted as metrologies of abrasive behaviors and removal force during polishing and cleaning processes As small as a diameter of 50nm silica particle can be individually detected and spatial distribution of particles in three dimensional space also clearly observed using the fluorescent microscopy...
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