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This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-of-the-art RSP performance. By realizing <100> channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from...
In this paper, we present a new approach to integrate in a 0.35 μm BCD technology, low Ron LDMOS power transistors with highly competitive Specific Resistance figure of merit (Rsp, defined as Ron∗Area). The LDMOS are fully isolated in order to support applications which may bias the source/drain electrodes below the substrate potential, which is critical for devices used in high-current, high-frequency...
In the direct-water-cooled power module, there is a small gap between the heatsink and the channel wall. This gap results in bypass flow that reduces the pressure drop while maintaining high heat transfer. In this paper, we discuss the effect of this gap on both pressure drop and heat transfer over pinfin heatsinks using our semi-analytical model based on mass, momentum, and energy conservation within...
AlGaN/GaN high electron mobility transistors (HEMTs) are one of the prospective candidates for high switching frequency power electronics applications thanks to its wide band gap (3.4eV), high breakdown voltage, large critical electric field, high carrier mobility, and the inherent high speed characteristics. With the high power densities that AlGaN/GaN HEMTs are capable of reaching, heat dissipation...
We developed the direct-liquid-cooling IGBT module which enabled downsizing of a power control unit for HEV system and high reliability simultaneously. This module eliminates thermal grease by unifying a ceramic substrate and a heat sink. It contributes this module realized the reduction of thermal resistance 30 % compared to the conventional indirect liquid cooling type. High thermal conductive Si...
This paper demonstrates a new phenomenon for the state-of-the-art ultra-high density trench power MOSFET: channel conduction during dynamic avalanche even when gate voltage is well below the nominal threshold voltage. In particular, a comprehensive study has been done through mixed-mode 2D device simulation and measurement, showing that the channel conduction during avalanche can not only strongly...
A novel low-side structure based on the optimum variation lateral doping (OPTVLD) technique, which is formed by many inner VDMOS cells combining an outermost LDMOS, is realized in the 0.8μm BiCMOS-compatible technology. With the benefit of the additional vertical cells, it presents a low specific on-resistance with high breakdown voltage, which significantly advances the prior art. Furthermore, since...
This paper presents a circuit design and efficiency study for integrated converters with switching frequencies up to 15 MHz at high conversion ratio with input voltages up to 40 V and output voltages <5 V. An asynchronous buck converter is well suitable, while in contrast, a synchronous topology causes larger switching losses due to its low side switch. Critical design aspects are presented along...
The possible different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in IGBTs is analyzed in this paper. Experimental measurements conducted on different commercial devices show that, at high peak current, the UIS limit moves from energy limitation to current limitation. This current driven failure mode is not well assessed in literature. In this...
Novel 200V power devices, including the n-type lateral insulator gate bipolar transistor (nLIGBT), the n-type lateral extended drain MOS (nLEDMOS) and the p-type lateral extended drain MOS (pLEDMOS), have been fabricated by using the special 0.5μm inverted HV-well SOI technology. All the novel devices own larger current density, higher off-state breakdown voltage (BV) and better hot-carrier reliability...
This study shows, for the first time, possibility of very shallow junction termination in submicron scale. The 2D-TCAD simulations unveil even 0.2μm junction depth structures are capable of blocking 1200V and usability for power devices with more than two hundreds of guard rings. Very shallow structure has robustness against diffusion depth deviation by special guard ring arrangement.
A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with anti-parallel Shockley diode is proposed. By introducing an additional isolated p-n junction at the anode, the effect of anode-short is eliminated, and accordingly, the snapback problem is solved in the novel RC-IGBT. The snapback-free characteristics can be realized in a single cell with a width of less than 10 μm. Besides,...
A current distribution model is presented for the RC-IGBTs both at IGBT mode and DIODE mode. According to the analytical model, smaller cell size would be better for the distribution of the current density and full utilization of the silicon, but the snapback would be worse. Then a novel RC-IGBT with a floating P-plug is proposed and investigated by simulations. The results show that it can suppress...
The tridimensional channel SOI-LIGBT on 1.5μm thin SOI layer is developed in this paper. The key feature of the device is that there are numerous separated P-body cells located in the emitter region, which can increase the efficient channel width, enhance electron injection and attain a large current capability. The proposed SOI-LIGBT exhibits the current density of 150A/cm2, which has an improvement...
Measurements show that the IGBT is able to clamp the collector-emitter voltage to a certain value at short-circuit turn-off despite a very low gate turn-off resistor in combination with a high parasitic inductance is applied. The IGBT itself reduces the turn-off diC/dt by avalanche injection. However, device destructions during fast turn-off were observed which cannot be linked with an overvoltage...
A novel IEGT (Injection Enhanced Gate Transistor) design for drastically reducing of gate capacitance has been proposed in this work. The device structure named IEGT-TSE (IEGT with Trench Shield Emitter) has a dummy trench electrode connected to an emitter electrode. It shields gate electrode from floating p-well during switching. To demonstrate this effect, we exhibit switching waveforms by a numerical...
A trench shielded planar gate IGBT is proposed in this paper. The unique 3D top cell structure, combining high density trench and low channel density, offers an excellent conduction vs. switching loss trade-off and a significantly better Short-circuit SOA compared to trench IEGTs. Measurements on fabricated devices show a 0.1V lower VCESAT for the same Eoff, and a 2x improvement in short circuit SOA.
A 4H-SiC trench MOSFET has been developed that features the use of trench gates with a thick oxide layer on the bottoms of the trenches for relieving the electric field strength of the gate oxide layer. The maximum electric field strength and gate-drain charge (Qgd) of this device is 46% and 38% lower than that of a conventional MOSFET, respectively. A □5mm chip was fabricated with a thick oxide layer...
This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated...
We present a new concept in insulated-gate bipolar transistor (IGBT) gate drivers with a blocking voltage up to 3.3kV that have a pulse transformer interface and a function for self-adjusting active gate control. The error-correcting decoder we proposed contributed to the reliability of signal transmission. Moreover, the method of gate control using differentiation of gate voltage could automatically...
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