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We present an extension of Duato's necessary and sufficient condition a routing function must satisfy in order to be deadlock-free, to support environment constraints inducing extra-dependencies between messages. We also present an original algorithm to automatically check the deadlock-freeness of a network with a given routing function. A prototype tool has been developed and automatic deadlock checking...
Invariants in sequential circuits could be very useful for sequential optimizations and for speeding up functional verification tasks. However, the lack of efficient and scalable invariant identification tools limits their usage. In this paper, we present a new tool, IChecker, for efficient identification of true invariants for any given initial set of invariant candidates. ICheker uses new circuit...
Summary form only given. Assertion based validation of hardware and software systems has been in use in the industry for a long time. In the software languages such as C++ or Java, there are special assert constructs that are used to specify a Boolean condition. These conditions express what the programmers think ought to hold, at specific points in their programs. Violations of such assertions provide...
As embedded systems have become pervasive and ubiquitous in contemporary technologies, their development requires highly reliable design approaches. One of these approaches is the so-called synchronous programming paradigm, where its mathematical basis provides the required formal concepts to satisfy correctness expectations. Among these synchronous programming concepts, the multi-clocked model of...
Equivalence checking is one of the most important issues in VLSI designs to guarantee that bugs do not enter the design during optimization steps or synthesis steps. In this paper, we propose a new word-level equivalence checking method between two models before and after high-level synthesis or behavioral optimization. Our method converts two given designs into RTL models which have the same datapath...
SystemC has gained popularity as a modeling language in the design of highly complex, heterogeneous, and large concurrent systems. Efficient and accurate simulation of the SystemC designs has become increasingly important. In this paper, we analyze the synchronization dependencies of concurrent systems modeled in the SystemC environment, where SystemC models are simulated through a discrete event...
Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sophisticated automation is mandatory. We describe how a model-based test generation technology was integrated into the verification flow of a configurable...
Transaction level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems design and verification. It allows designers to focus on the functionalities of the design, while abstracting away implementation details that are added at lower abstraction levels. A TLM-based design flow can afford several advantages, such as, TLM-RTL mixed simulation,...
Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is...
Summary form only given. Ever increasing design sizes and the need for more sophisticated fault models at smaller process geometries require the use of compression technology to reduce the size of the ATPG pattern set. Otherwise those don't fit on the automated test equipment. Compression is becoming the norm on the most advanced chips and is the enabling technology for true at speed testing of very...
A testable implementation of bit parallel multiplier over the finite field GF(2m) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2m) multiplier circuit, is also presented. Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool. The test complexity is lower than ATPG generated...
Functional verification is a complex and time-consuming task in the design process. Recently, various approaches have been developed to improve verification efficiency, including advanced coverage analysis techniques, coverage-driven verification methodologies and coverage-directed stimulus generation techniques. One remaining challenge is to fully automate functional coverage closure. This paper...
Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and emerging...
Functional verification is a major challenge in the hardware design development cycle. Defining the appropriate coverage points that capture the design's functionalities is a non-trivial problem. However, the real bottleneck remains in generating the suitable testbenches that activate those coverage points adequately. In this paper, we propose an approach to enhance the coverage rate of multiple coverage...
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using three different approaches, an exact one, an approximated one that ignores the correlation between state variables and a third that only takes into account correlations within pre-defined groups that are formed based on an originally...
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