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Increasing the productivity of simulation-based semiconductor design verification is one of the urgent challenges identified in the International Technology Roadmap for Semiconductors. The most difficult aspect is the generation of stimulus for functional coverage closure. This paper introduces a new Coverage-Directed test Generation (CDG) feedback loop which applies Inductive Logic Programming (ILP)...
Functional verification is a complex and time-consuming task in the design process. Recently, various approaches have been developed to improve verification efficiency, including advanced coverage analysis techniques, coverage-driven verification methodologies and coverage-directed stimulus generation techniques. One remaining challenge is to fully automate functional coverage closure. This paper...
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