Functional verification is a major challenge in the hardware design development cycle. Defining the appropriate coverage points that capture the design's functionalities is a non-trivial problem. However, the real bottleneck remains in generating the suitable testbenches that activate those coverage points adequately. In this paper, we propose an approach to enhance the coverage rate of multiple coverage points through the automatic generation of appropriate test patterns. We employ a directed random simulation, where directives are continuously updated until achieving acceptable coverage rates for all coverage points. We propose to model the solution of the test generation problem as sequences of directives or cells, each of them with specific width, height and distribution. Our approach is based on a genetic algorithm, which automatically optimizes the widths, heights and distributions of these cells over the whole input domain with the aim of enhancing the effectiveness of test generation. We illustrate the efficiency of our approach on a set of designs modeled in SystemC