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Plasma etch in semiconductor chip manufacturing is a complex process. The final process performance depends strongly on process parameters and their distributions at the surface of production wafers in an etch chamber. Until recently, there was no known technique that could monitor such critical parameters in-situ at the wafer surface before. In this paper the authors discuss an innovative technology...
The thermal conduction in ultra-thin single crystal silicon layers has a strong influence in self-heating of deep submicron transistors. Precise measurements of lateral thermal conductivity of single crystal silicon layers have great importance for thermal model construction of submicron transistors. The traditional steady-state joule heating method is improved by inducing symmetric structure and...
Due to decreasing supply voltages and increasing power consumption of today's VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during floorplanning stage in the today's physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floorplanning for efficiently minimizing the worst-case IR drop subject to limited routing resource...
Utilizing a novel unit-gain compensation cell (UGCC) to perform frequency compensation and power supply rejection (PSR) enhancement, a low-voltage high-PSR low-dropout regulator (LDO) is presented in this paper. The proposed UGCC, consisting of a 1 pF on-chip capacitor and six transistors, effectively overcomes the drawbacks that exist in the conventional compensation schemes by generating an internal...
This paper describes a low offset high precision curvature compensated bandgap reference in a 0.5-mum n-well CMOS technology without resistors. This bandgap reference employs an inverse function voltage transfer cell rather than conventional resistors, together with a low-noise and low-offset scheme to provide a temperature independent gain. Cascode structures are also introduced in order to improve...
This paper presents a design and an implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35 mum CMOS technology. Due to the differential transmission technique and the low voltage swing, low-voltage differential signaling (LVDS) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS...
A digital circuit with self-repairing characteristic based on embryonic cellular array, which attempts to draw inspiration from the biological process of ontogeny, to implement novel digital computing machines endowed with better hardware fault-tolerant capabilities is researched in this paper. The self-repairing digital circuit (SDC) consists of the two-dimensional electronic cellular array, the...
In this paper an all digital phase-locked loop (ADPLL) that is based on double edge triggered D-flip-flops (DETDFF) was proposed. By using DETDFF, the functions of bi-directional zero crossing sample and phase detection, which are key issues in the designing process of ADPLL with several new important characteristics, were implemented. In addition, the run speed of each part in the loop was enhanced...
This paper presents a 10-GHz-band LC-tank voltage-controlled-oscillator (VCO) designed for high-frequency and low-phase-noise operation using commercial 0.18-mum CMOS technology. The complementary cross-coupled differential topology is adopted in the design in order to reduce phase-noise. The simulated phase-noise are of -90.1 dBc/Hz and -112 dBc/Hz at 100kHz and 1MHz offset frequency respectively,...
An improved error amplifier with initial voltage reference for power management applications is presented in this paper. Based on the structure of LDO, a simple structured and high integration voltage regulator by optimizing the circuit topology is accomplished. The characteristics of the improved error amplifier are simulated by using Hspice and Samsung Bipolar Process BCH4 device models. It achieves...
Switch capacitor integrator circuits for dual-ramp-single-slop analog to digital converter (DRSSADC) is designed. The switch capacitor integrator uses a fully differential topology combined with input-to-output class AB amplifier and improved switch. Using the methods of Monte Carlo analysis and HSPICE simulation, the paper emphasizes to present design of the amplifier. Based on CSM 0.35mum CMOS process,...
A high precision voltage regulator was proposed. It can work under the supply voltage from 8V to 20V. Compared with conventional regulators, its performances were improved by boosting the feedback loop gain, minimizing the effect of base width modulation and base current error correction. Simulation results showed the line regulation of 33muV/V and load regulation of 30muV/mA was achieved. And by...
A 3.1-10.6 GHz ultra wideband (UWB) low noise amplifiers (LNA) was designed in 0.35-mum SiGe BiCMOS technology. The circuit technique of multiple feedback loops was adopted to achieve the matched input terminal impedance and wide bandwidth simultaneously. In the focused band this LNA has a peak gain of 19dB with a ripple of less than 2dB, an input return loss of less than -12dB and a noise figure...
Fast and accurate calculation of interconnect parasitic parameters is becoming an important research issue of the IC design field. A hierarchical h-adaptive method based on direct boundary element method (BEM) with quasi-multiple medium (QMM) acceleration is proposed for the VLSI parasitic capacitance extraction. The adaptive method with h-type mesh refinement ensures high accuracy, while applying...
A fast interconnect capacitance extraction engine is realized and presented here. Employing a fast multipole accelerated generalized minimal residual (GMRES) based three-dimensional (3-D) field solver, this software tool can quickly and accurately extract parasitic capacitances of arbitrary interconnects embedded in piece-wise constant dielectrics. This engine is also capable of performing fast and...
This paper presents an on-chip dynamic trace design method which is very useful for the real-time dynamic trace of the program executing process of embedded microprocessors. We introduce an on-chip tracer (OCT) module to fulfill this dynamic tracing task by setting watchpoints at some locations of user program in order to trace and output the information on these spots. As a result, debugger can find...
As microelectronic circuits become smaller, inter-metal insulators in the circuits need to have lower dielectric constant (low-k) for preventing signal delays and cross talks. Theoretical studies on the mechanical and dielectric properties of low-k films of silicon oxycarbide materials (SiOCH) are highly desired. In the paper, we used a new method to investigate SiCOH film's properties at the atomistic...
AlN thin films with high c-axis orientation are deposited by DC reactive magnetron sputtering and active feedback control system. Based on the analysis of the Berg hysteresis model, the authors analyze the technology parameter influence on the hysteresis effect, including pumping speed, temperature of substrate and target, input power, target to substrate distance and area of target. A new active...
With the development of microprocessor, large-storage and high-speed memories are required to keep up with it. Since the conventional simulation of memory is extremely time-consuming, a new performance model focusing on fast delay simulation of SRAM is presented in this paper. This simulation model is accurate and fast, validated by cadence simulation tool, it effectively solves the simulation difficulties...
Based on the improved approximation of modified triangular potential well, a physical-based model of MOSFETs threshold voltage as well as its analytical formulation, considering quantum effects in strong inversion layer, is presented. The new model accounts for quantum effects for future generation MOS devices and integration circuits. The calculated results of the improved model obtained from this...
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