Switch capacitor integrator circuits for dual-ramp-single-slop analog to digital converter (DRSSADC) is designed. The switch capacitor integrator uses a fully differential topology combined with input-to-output class AB amplifier and improved switch. Using the methods of Monte Carlo analysis and HSPICE simulation, the paper emphasizes to present design of the amplifier. Based on CSM 0.35mum CMOS process, the amplifier achieves high voltage gain and broad frequency band response under 3 V supply voltage, which consumes only 125 muW, achieving 74 dB open-loop gain, 8 MHz unity gain band width and 80deg phase margin for a load capacitance of 5 pF. And the integrator requires only 225 muW of power to meet the DRSSADC requirements