This paper presents a design and an implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35 mum CMOS technology. Due to the differential transmission technique and the low voltage swing, low-voltage differential signaling (LVDS) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a differential amplifier. This circuit is operated up to 2.5 Gbps with random data patterns. The circuit has the power consumption of 21.04 mW