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This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules...
Carry select adder is fastest adder but it required more area and power. The modern VLSI design systems are small in size and less power consumption so the modification is need in the carry select adder to achieve the reduced area and less power consumption. Two proposed works are introduced in thispaper. First method include the reduction of area and power in Carry select adder by modifying the EX-OR...
This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules...
This paper proposes the design of an energy efficient, high speed and low power full subtractor using Gate Diffusion Input (GDI) technique. The entire design has been performed in 150nm technology and on comparison with a full subtractor employing the conventional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), respectively it has been found that there is a considerable...
This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses...
This paper presents an orchid disease detection system using image processing and fuzzy logic. The main objective of this paper is to design a system that is able to detect an orchid disease by processing its leaf image. The system consists of two parts, image processing and fuzzy logic. The leaf image processing uses methods like grayscaling, threshold segmentation and noise removing. The data collected...
This paper presents some proposed and new techniques in comparison to a traditional one for register-transfer level (RTL) circuits. The traditional technique focuses on killing glitches in both the control and data path parts of the circuit to reduce power consumption. By analyzing and simulating the generation and propagation of glitches in some benchmark circuits, we found out some issues when killing...
SURF is a well-known scale- and rotation-invariant feature detection algorithm, and it has been widely used for many object tracking algorithms. But it is hard to implement it in real time due to its high computational complexity. In this paper, the hardware architecture of SURF IP was proposed for real time operation. Especially its block memory usage was greatly reduced by partitioning the SURF...
The proliferation of multi-core and many-core chips for performance scaling is making the Network-on-Chip (NoC) occupy a growing amount of silicon area spanning several metal layers. The NoC is neither immune to hard faults and transient faults nor unaffected by the adverse increase in hard faults caused by technology scaling. The ramifications for the NoC are immense: a single fault in the NoC may...
The current systems are very complex and feature a high degree of communications. Because the bus is a critical and shared resource, it can no longer cope with the requirements of applications for which the bandwidth is a critical parameter. An intermediate solution was to use cross-bars but was also rejected in favor of more interesting solutions: using a network on chip (NOC) in order to meet the...
The advantages of simultaneous read and write operations for dual-port SRAM memory cells are well known. In this paper two configurations of dual-port 8-Transistor Differential (8T-D) and 7-Transistor Single End SRAM cells are presented. The benefits of power-delay product and power dissipation are verified. The goals of low power and high performance control of the full CMOS SRAM can be achieved...
Interpolation and Decimation is very effective and popular in multirate signal processing applications. This paper proposes a high speed, area and power efficient VLSI architecture for polyphase decimation filter with decimation factor of three (D=3) using BFD (Bypass Feed Direct) multiplier. Various key performance metrics such as number of slices, maximum operating frequency, number of LUT's, input...
The paper describes the power and area efficient carry select adder (CSA). Firstly, CSA is one of the fastest adders used in many data-processing systems to perform fast arithmetic operations. Secondly, CSA is intermediate between small areas but longer delay Ripple Carry Adder (RCA) and a larger area with shorter delay carry look-ahead adder. Third, there is still scope to reduce area in CSA by introduction...
In the last decade, the field of microprocessor architecture has seen the rise of multicore processors, which consist of the interconnection of a set of independent processing units or cores in the same chip. As the number of cores per multiprocessor increases, the bandwidth and energy requirements for their interconnection networks grow exponentially and it is expected that conventional on-chip wires...
This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time...
Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. Design of multiplier is done, considering the tradeoffs between low power and high speed. The Braun's multiplier is one of the parallel array multiplier which is used for unsigned numbers multiplication. The dynamic power and delay of the Braun multiplier...
In this paper, we present a comprehensive study of Medium Access Control (MAC) protocols developed for Wireless Body Area Networks (WBANs). In WBANs, small battery operated on-body or implanted biomedical sensor nodes are used to monitor physiological signs such as temperature, blood pressure, ElectroCardioGram (ECG), ElectroEncephaloGraphy (EEG) etc. We discuss design requirements for WBANs with...
Power Optimization is essential part of early design planning stage besides performance. The blooming of mobile applications era further drive the need for power reduction in SOC design. Though SOC designers can opt for commercial EDA tools for concurrent timing, power, noise optimization, a thorough leakage, performance, area trade off analysis is required during design definition phase to ensure...
The area-based localization algorithms use only the location information of some reference nodes, called anchors, to give the residence area of the remaining nodes. The current algorithms use triangle, ring or circle as a geometric shape to determine the sensors' residence area. Existing works suffer from two major problems: (1) in some cases, they might issue wrong decisions about nodes' presence...
This paper explores a variation of the Han-Carlson adder for large word sizes and compares the performance of the new design with the traditional design. This work introduces a second type of design with two Brent-Kung stages each at the beginning and at the end and with Kogge-Stone stages in the middle, henceforth referred to as the “Hybrid Han-Carlson design.” With the new design, the Hybrid Han-Carlson...
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