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We review a silicon photonics platform that integrates low-loss passive components with high-speed modulators and photodetectors operating at 50Gb/s from CMOS compatible voltages.
We review our nanosecond-scale switch technology in IBM's 90nm photonics-enabled CMOS process. We present low-insertion-loss, low-crosstalk, and low-power broadband optical switch fabrics that monolithically integrate the photonics with the CMOS electronics.
An ultra-wideband low noise amplifier is presented in this paper. The current-reuse technique is used to get the desired results with lower power consumption. Input impedance matching of 50 Ω is provided by a common-gate through resistive feedthrough stage all-entire the 3–11GHz band of interest. Second stage is used to get a good flatness and high conversion gain. Simulation results in TSMC 180nm...
This paper proposes a technique for determining the position of a moving vehicle using LED street lights and a CMOS sensor camera. In this system, LED street lights transmit their identification codes to a camera attached on the vehicle. Then, a single view geometry technique is used to determine the position of the camera. Normally, the high speed of the vehicle combined with the rolling shutter...
A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering...
A new authentication and security system together with a nano-key concept using optical variable nanostructures (OVNs) are introduced. The three proposed designs are 1) the passive authentication, 2) the active authentication, and 3) the nano-key authentication. The passive authentication is obtained by insertion of an OVN image divided between multiple layers of the fabrication process. Authentic...
We demonstrate an optical link operating in indoor ambient lighting conditions using a CMOS single photon avalanche diode (SPAD) optical receiver and a RGB light emitting diode (LED). The high sensitivity of the SPAD receiver allows the link to operate at 2 m distance at a total 60 Mb/s and bit error rate (BER) of 1×10−3 without lensing. The transmitter implements color shift keying (CSK) using a...
A low complexity high speed generalised space shift keying (GSSK) visible light communication (VLC) link is investigated. A 2 × 2 Gallium Nitride (GaN) micro-LED array is used as transmitter and a complementary metal-oxide-semiconductor (CMOS) avalanche photo-diode (APD) array working as receiver. A bit error ratio (BER) of 2 × 10−4 up to a data rate of 320 Mbits/s is achieved which allows for error-free...
Stochastic processes are ubiquitous and the stochastic differential equation is a formal setting to analyse dynamic circuits in noisy environments. Initially, Norbert Wiener developed stochastic integral to prove the nondifferentiability of the Brownian motion with probability one. Later, it was utilized by Kiyoshi ItΣ to construct stochastic differential rules. This paper discusses two Theorems....
Arrays of GaN light-emitting diodes can be used for rapid display of pattern sequences or high speed parallel data transmission using different sites of the array. These operation modes can be combined with each other and are useful for light-fidelity networks with Gb/s capacity.
The paper presents eight transistors SRAM cell with improved noise (interferences) immunity. The effect is reached by use an additional bus to control the state of the cell trigger. The results of the simulations as well as experiments have been demonstrated. The following SRAM characteristics have been obtained SNM = 222 mV, WRM = 1017 mV, the cell discharge current is 114 uA. The test chip has been...
This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted time keeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultra-low power operation in 0.18 µm CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [−40°C...
In this work a new structure of current mode min-max circuit using 0.18µm. CMOS standard technology is presented. It is based on cascode current mirror and enjoys 30 NMOS transistors. A 1.8(V) power supply is applied and simulation results are prepared using HSPICE software with level 49 parameters (BSIM3v3). It has noticeable advantages like 0.9 percent error in maximum input signal amplitude, 0...
We have investigated strain effects on the electrical conductivity of bulk GaSb and GaSb(111) films. For the biaxially-strained bulk systems, the electrical conductivity becomes highest at normal pressure and temperature for lower hole concentration. As the hole concentration becomes larger, the singularity of the electrical conductivity at normal pressure disappears. Such behaviors originate from...
This paper reports a novel differential Colpitts LC oscillator circuit topology designed in 28 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. It exploits magnetic coupling between the spirals of the LC tank, in order to enhance the equivalent quality factor (Q). The oscillator circuit topology presented here shows a potential for achieving a high spectral purity at the mm-wave frequency...
This paper reports a novel voltage-controlled oscillator (VCO) circuit topology based on a transformer-coupled π network. As a case study, the proposed VCO circuit topology has been designed and studied for 60 GHz applications for emerging 5th generation wireless communications. Overall, the presented VCO circuit topology is characterized by low phase noise (−91 dBc/Hz at a 1 MHz frequency offset...
This paper presents an implementation of a binary pulse-position modulator (2-PPM) for impulse-radio ultra-wideband (IR-UWB) systems, capable of producing an appropriate signal to drive the final output stage of an ultra narrow pulse generator. Compared to the usual circuits based on voltage-controlled delay lines, this novel scheme uses digital signal processing of the clock and data signals with...
We have investigated CMOS photonics based on heterogeneous integration of SiGe/Ge and III–V semiconductors on Si, which gives us opportunities to enhance functionalities of Si photonics through their superior material properties for electronic-photonics integrated circuits.
In this paper we exploit the gm over ID methodology to optimize the design of a four stage conventional Distributed Amplifier (DA) for an Ultra-Wide Band positioning system. The W/L ratio and the DC-biasing of the amplifier's transistors are determined according to the gm over ID methodology by using a series of lookup tables generated starting from the model of the devices. The DA was designed using...
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