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This paper reports on a 1Mbit (128Kword × 8bit) SRAM using an advanced CMOS process technology. The typical address access time of 44ns and chip-select access time of 46ns are achieved with the power dissipation of 80mW for 1MHz operation. This SRAM employs a column DC bit-line load control to reduce power dissipation in the write mode operation. It also has an additional testing mode to access 4byte...
In the conventional array multiplier, the multiplication speed is restricted by the carry propagation. On the other hand, it is difficult to realize a compact multiplier in the high-speed multiplier such as the Wallace tree multiplier, because its layout is complicated and a large area is required for the interconnections. In such situations, the use of multiple-valued logic in conventional digital...
The performance limitations of the single cell FAMOS transistor have hindered the development of high speed MOS EPROM's that can match Bipolar PROMs for speed. Previous approaches to high speed MOS EPROMS have centered around a 4-T 11 I or a 2-T cell with It's inherent die area disadvantage and, hence, resulted in their manufacturable densities being limited to under 64K.
Recently, in the field of the nonvolatile memories, the demand for OTP-ROM (One Time Programmable-ROM) devices has been rapidly increasing. The OTP-ROM is an EPROM enclosed in a plastic package. From the market research, EPROMs are programmed only once in many cases. If an EPROM is enclosed in a more inexpensive plastic package rather than a package with a window for UV (Ultra-Violet) erasure, it...
Using active feedback technique an analogue four quadrant multiplier-divider presented in this paper has achieved a great dynamic range both at inputs and at the output, and a good linearity with nonlinearity error smaller than 2%. Moreever the circuit has a better independence from the manufacturing process and the geometrical size of MOS transistors.
Recently, several CMOS PLDs were reported using nonvolatile memory technologies for array implementation. However, the architecture of these CMOS PLDs are limited in only one programmable array feeding into a group of fixed OR gates. Therefore, the efficiency of its logic integration is greatly limited due to lack of product term sharing capability. This paper will describe a 25ns, 50mA CMOS Programmable...
Unlike memory applications where a repetitive cell is used and a relative insensitivity to faults is obtained through redundancy, the optimization task of a designer for large logic chips is very complex. To date most of the design optimization for yield is done by minimizing the chip area and usage of preestablished design rules. Based on the existing framework of yield calculation (1–2), we have...
CMOS DRAMs which were first introduced commercially in the 256Kb DRAM generation have proven their advantages in power and performance, and are expected to be the future trend. In CMOS DRAMs, the half-VDD bitline sensing scheme — is widely used in the current generation of 1 Mb DRAMs. However, the half-VDD sensing scheme suffers a performance degradation as VDD is reduced. Starting with the 4 Mb DRAM...
Introduction. Fast CMOS ECL interfaces offer important savings in off-chip delays for high speed CMOS SRAM, especially for sub-10 ns accesses in high speed large system applications. Asynchronous CMOS differential amplifier circuits in a 1 μm 5V technology [1] can meet the joint requirement of high speed and light tolerances needed for ECL receivers [2J.
The era of application specific ICs is stirring demand for that mixed analog and digital functions. At the same time, modern EDPs from personal computers to main frame computers are requiring faster, denser but less power consumped ICs.
A high speed circuit with precharged technology is described, k 32-bit ALU which employs this technology has been designed. New ALU realized about 2.5 times faster speed than that of former one which was designed by poly-cell technology, A carry-propagation delay time by the carry-lookahead and the conditional-sum was 5.0ns, which is 3.6 times faster than that of poly-cell approach. This technology...
In the development of high density DRAMs such as 1 M bit or beyond, it will be increasingly important to achieve high speed, competitive to SRAMs, in addition to low cost per bit. Recently, BIPOLAR CMOS (BICMOS) technology has been proposed for achieving high speed and low power operation, especially SRAMs (1,2).
The conversion time for high-speed analog-to-digital converters is limited by the rate at which the internal comparator(s) can amplify small voltages 1 into logic levels. Several comparators have been designed with response times of less than 10 ns [1,2]. However, these circuits are usually fabricated with bipolar transistors.
We review technology advancement in our three generations of coherent DSP implemented with 40, 20, and 16-nm CMOS technologies. The latest 16-nm implementation achieves sub-10-watt per 100 Gb/s transport for emerging data-center interconnect application.
A photodiode with 0.44 A/W has been fabricated in the Global Foundries 45 nm 12SOI process — a twenty times increase over previous results. The photodiode consists of a ring-resonator with ring-shaped silicon-germanium.
We present poly-silicon depletion-based optical modulators realized in a 65 nm CMOS platform for monolithic integration with electronics. Speeds up to 12.5 Gbit/s can be achieved with 5 dB insertion loss and 2.3 dB extinction ratio.
Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here we examine 25 Gb/s applications in the context of integrated transistor performance and demonstrate a 4λ×25 Gb/s reference design.
A wire-bond packaged ring-based CMOS silicon photonic transmitter with an asymmetric differential driver in 28nm CMOS is demonstrated operating at 50Gb/s NRZ with over 5dB dynamic extinction ratio and 610fJ/bit energy efficiency.
We demonstrate wavelength locking of a silicon ring modulator across 480pm laser wavelength drift using a drop-port OMA monitoring CMOS circuit and a dithering-based feedback loop at a settling speed of up to 380pm/s.
2.5D silicon interposer, for a cost effective optoelectronic package, is proposed and fabricated on a wafer level. Using this packaging approach, the fully assembled 120 Gb/s transmitter is scaled down to 6mm × 7mm.
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