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Pleasingly parallel algorithms such as filtered back-projection have been documented to enjoy significant speedups when ported to run on a graphics processor instead of a standard CPU. Presented here is a two-dimensional SAR backprojection implementation for a single GPU using the NVIDIA CUDA framework. Given that input range projections may be too large to fit in graphics memory, our implementation...
This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times...
This paper has presented and designed a four-channel video data system of reception, extraction, display and switch based on the DE2-70 development and education board and the development environment of embedded operating system μClinux. First, it received the video data packets, which were 640×480 resolution and RGB format coming from the four cameras in front-end through the router on network, and...
This paper presents a scalable H.264/AVC deblocking filter architecture based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. Architectural scalability to adapt to different users' requirements intelligently is demonstrated through dynamic self-reconfiguration on the reconfigurable...
In this paper, 3D image segmentation is implemented on Field Programmable Gate Array (FPGA) hardware. Segmentation is performed using the EM/MPM Bayesian algorithm. This algorithm segments 3D images using neighboring pixels in a Markov Random Field (MRF) clique. We have implemented this iterative algorithm in Xilinx FPGA, and have achieved greater than 100 times improvement over standard desktop computing...
In this paper, we propose a hardware implementation of H.264 intra frame encoder to achieve the real-time operation for video conference applications. The H.264 intra frame encoder is composed by intra 4×4 prediction, intra 16×16 prediction, integer transform, quantization (AC & DC), inverse integer transform, inverse quantization (AC &DC), hadamard, and inverse hadamard transform. This method...
In order to solve the compute-intensive character of image processing, based on advantages of GPU parallel operation, parallel acceleration processing technique is proposed for image. First, efficient architecture of GPU is introduced that improves computational efficiency, comparing with CPU. Then, Sobel edge detector and homomorphic filtering, two representative image processing algorithms, are...
The coding gains of the H.264/AVC video encoder, come from the improvement of the prediction method for intra and inter prediction in goal to achieve best image quality. However, their enormous computation, high complexity and the dissipated power are the main penalties. The approach proposed in this paper invests and exploits the best hardware solution for intra and inter prediction. Intra prediction...
In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII...
The multi-angle spectro-polarimetric imager (MSPI) is an advanced camera system under development at JPL for possible future consideration on a satellite based Aerosol-Cloud-Environment (ACE) mission as defined in the National Academies 2007 Decadal Survey. The MSPI project consists of three phases: Ground-MSPI, Air-MSPI, and Space-MSPI. Ground-MSPI is a ground-based demonstration focused on characterizing...
An edge-flag rendering algorithm for supersampling antialiasing with low hardware cost is presented. The proposed algorithm works differently from the common rendering algorithm, using only one counter per pixel instead of one counter per sample point. Compared to the common rendering algorithm, the proposed one uses about 83% less memory capacity for a scanline-sized buffer and saves nearly 65% of...
This paper presents the implementation of a face detection algorithm on FPGA for an eye mouse control system. An improved algorithm of skin color module and binary image projection is used to ensure real-time detection. The system is based on a hardware/software co-design, which consists of a dedicated hardware accelerator that solves the parts of the algorithm with higher computational cost and an...
Cellular Neural Networks (CNN) [1] main assets are quoted to be their capacity for parallel hardware implementation and their universality. On top, the possibility to add the information of a local sensor on every cell, provides a unique system for massive parallel signal processing responding in hardware time. Image processing has been, for a long time, the main field where the community has focussed...
A parallel unified processor for graphics and vision is developed. It achieves 371.9G0PS/W in full operation through a 6-way VLIW datapath, reconfigurable processing elements for graphics and vision mode, and a pixel arranger for data-level parallelism. The pose-estimation engine achieves 0.89 μW/fps for marker-based augmented reality.
Cellular Nonlinear Networks (CNN) establish a theoretical framework in which programmable focal-plane image processing arrays can be developed. The conventional support for its analog programmability in VLSI is the implementation of transconductor-based multiplication of the input, output and state variables times the corresponding template elements. However, some distributions of weights can be greatly...
A novel approach for counting people passing through a region where is surveilled by a parallel-fixed binocular camera is proposed in this paper. Firstly, two virtual counting lines are set to obtain four line space-time gray images. Then an integrated algorithm based on binocular stereovision and regional gray projection is proposed to extract and split overlapped moving objects in complex counting...
Image filtering is mainly used for pre-processing in many applications of image processing such as noise removal in industrial inspection, enhancement for pattern recognition, restoration of degraded images, etc. For real-time processing, it is crucial that these applications meet the desired throughput. As processing demands get higher through complex algorithms and large resolution or very high...
FPGA based hardware accelerators have been more and more widely used in different kind of applications. As compared to other solutions and the direct hardware implementation, the advantage of the FPGA devices is their flexibility that arises from their programmable nature. In addition to this, some FPGA devices also support partial dynamic reconfiguration. When general purpose processors and reconfigurable...
Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from photographs that capture reality for a short period of time. They are renewed and transmitted at a rate of 25-30 frames per second, in a typical real-time scenario. Each of these frames needs to be filtered and processed in order to detect a feature on it. This processing...
Measuring a vehicle's speed using a video image is an important technique in an intelligent transportation system. This paper presents a hardware implemented vehicle speed measurement (VSM) system. The operation of the system consists of three steps. First, we remove vehicles from a series of captured images to create a background. To do this, we introduce a simplified exclusion algorithm optimized...
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