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As solid state drives (SSDs) are gradually replacing hard disk drives, error correction is critical to SSDs since NAND flash has deteriorating reliability over their life span. Existing error correction codes suffer from limited error correction capability or error floor issues. Polar codes are promising for SSDs since they are theoretically proven optimal codes and have good error floor behavior...
Suppose Alice and Bob share a secret key, of which Eve is initially oblivious. Clearly, Alice and Bob can use this key to ensure that any particular plain-message sent is both authentic and secure. This paper investigates how many plain-messages can be sent per bit of secret key, while still ensuring both secrecy and authentication. In particular the secrecy tolerance relates to the min-entropy of...
With a development of process technology, a memory density has been increased. However, a smaller feature size makes the memory susceptible to soft errors. For reliability enhancement, ECC with single bit error correction and double bit error detection is widely used. As multiple bit cell upset become dominant, there is a need for stronger ECC. ECC such as RS or BCH code requires significantly large...
We study energy harvesting (EH) transmitter and receiver, where the receiver decodes data using the harvested energy from the nature and from an independent EH node, named helper. Helper cooperates with the receiver by transferring its harvested energy to the receiver over an orthogonal fading channel. We study an offline optimal power management policy to maximize the reliable information rate....
This paper studies the one-sided secrecy of a full-duplex two-way wiretap channel. It is motivated by a practical communication scenario, where two legitimate users communicate with each other in the presence of an external eavesdropper and only one of the users wishes to keep its message confidential from the external eavesdropper for the sake of privacy. As a general result, we establish an achievable...
On — chip communication suffer from bit error especially at highly dense implemented system on chip. Reducing the rate of bit error in On-chip communication is carried out by error detection and correction codes. But it has its own limitation. So reconfigurable multiple code based system is suitable for heterogeneous system design. But selecting correct code for the correct subsystem or for current...
High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density...
In order to relieve reliability problem caused by technology scaling, LDPC codes have been widely applied in flash memories to provide high error correction capability. However, LDPC read performance slowdown along with data retention largely weakens the access speed advantage of flash memories. This paper considers to apply the concept of refresh, that were used for flash lifetime improvement, to...
External radiations create soft errors which are turning into an undeniable critical issue. Customarily, Single Error Correction (SEC) code which can detect and correct 1-bit error per memory word is used to rectify soft errors. As errors turn out to be more common, the SEC methodology becomes inefficient. In this paper, Horizontal-Vertical Parity and Diagonal Hamming (HVPDH) method is proposed for...
Recently, video traffic has rapidly increased, and a considerable portion of that is caused by wireless devices. Since video streaming services now require high data rates, IEEE 802.11 has been widely used to support them in the wireless environment. On the other hand, in densely populated areas (e.g., conference rooms), multiple video streaming services using a unicast method can result in exceeding...
Flash memory development through technology scaling and bit density has significant impact on the reliability of flash cells. Hence strong error correction code (ECC) schemes are highly recommended. With a strong error correction capability, low-density-parity code (LDPC) is now applied for the state-of-the-art flash memory. However, LDPC has long decoding latency when the raw bit error rates (RBER)...
Providing a high level of informational reliability and, firstly, noise immunity is the main problem of information channel (IC) synthesis. Quantitatively noise immunity is measured by reception outcome probabilities: probability of correct reception, false reception and protective failure. The most urgent problem of the IC noise immunity improvement is minimization of the false reception probability...
In this paper, a duality between wiretap and state-dependent channels with non-causal channel state information at the transmitter is established. First, a common achievable scheme is described for a certain class of state-dependent and wiretap channels. Further, state-dependent and wiretap channels for which this scheme is capacity (resp. secrecy capacity) achieving are identified. These channels...
We study a secure communication scenario in which the channel is under two classes of attacks at the same time: a passive eavesdropper and an active jammer. This scenario is modelled using the arbitrarily varying wiretap channel (AVWC), in which the channel varies from one channel use to the other. It has been shown that in general reliable communication over AVWCs requires some sort of coordination...
In this paper, we perform a simulated fault injection reliability assessment of memory centric flooded LDPC decoders affected by probabilistic storage errors. We investigate the error correction capability in terms of Frame Error Rate (FER) of faulty flooded Min-Sum decoder, under Binary Additive White Gaussian Noise (BiAWGN) channel model. We have injected all the memories, as well as only the memories...
We investigate the outage and decoding-delay performances for full-duplex (FD) decode-forward (DF) relaying with backward and sliding window decoding. In our analysis, we consider a block fading channel with full channel state information (CSI) availability at receivers and with limited CSI at transmitters. For backward decoding where the destination starts decoding from the last transmission block,...
In this paper, we analyze the performance of a single-relay network in which the reliability is provided by means of Random Linear Network Coding (RLNC). We consider a scenario when both source and relay nodes can encode packets. Unlike the traditional approach to relay networks, we introduce a passive relay mode, in which the relay node simply retransmits collected packets in case it cannot decode...
In this paper, we examine message prioritization in terms of both rate and reliability in the two-way relay channel using decode-forward relaying. Each source sends both a low priority message and a high priority message. We design a scheme that routes the high priority messages through the relay and direct link but the low priority message is only decoded by the destination. For fixed message priorities,...
The encroachment of technology grading — smaller dimensions, higher consolidation densities, and lower berth operating voltages — has come to a level that reliability of memory is put into jeopardy. Hence a novel approach is proposed to overcome this multiple cell upsets using error correction coding techniques. Recently, matrix computer code (MCs) based on senses of hamming codes have been proposed...
Real-time Audio/Video (A/V) collaboration is an application domain for which Cloud adoption is being investigated. However, the professional market generally prefers reliability over elasticity / scalability, in terms of managed delay and quality, and hence usually relies on dedicated specialized hardware and network setups, which are costly and hard to scale. This paper proposes cloud-enabled A/V...
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