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The Asymmetric Numeral Systems (ANS) are a family of entropy coders for information sources with a finite alphabet, developed by J. Duda as an alternative to arithmetic coding. We have already proposed an approximation formula to the stationary distribution of the states in a special version (ABS) of ANS. We show that our previous result in ABS, which deals only with binary sources, can be applied...
In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of inputs and outputs. In wireless communications Viterbi algorithm is employed to have minimal number of communication channels. The Viterbi decoder design at 65nm technology using reversible logic has made an attempt...
Providing a high level of informational reliability and, firstly, noise immunity is the main problem of information channel (IC) synthesis. Quantitatively noise immunity is measured by reception outcome probabilities: probability of correct reception, false reception and protective failure. The most urgent problem of the IC noise immunity improvement is minimization of the false reception probability...
Instruction set simulators (ISSs) are indispensable tools for developing new architectures and embedded software. Due to the increasing variety of architectures and time-to-market pressure, it is important to efficiently develop fast ISSs based on dynamic binary translation. However, the implementation of such ISSs needs more effort than interpretive ISSs. In this paper, we propose a novel framework...
The normal operation of many cyberphysical, biological, and neural systems fit naturally with robust control, with key variables like lane positions, voltages, temperatures, blood pressures, etc maintained within tight bounds despite diverse uncertainties. However, two challenges in particularly need further theory that this paper addresses. One is that control is distributed with communication having...
The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified...
We investigate the outage and decoding-delay performances for full-duplex (FD) decode-forward (DF) relaying with backward and sliding window decoding. In our analysis, we consider a block fading channel with full channel state information (CSI) availability at receivers and with limited CSI at transmitters. For backward decoding where the destination starts decoding from the last transmission block,...
Touchpads, haptics and gestures are becoming popular user-interfaces in modern electronic gadgets. In this project, we propose to use a touch pad to construct a HAM radio interface. Low-power, short-range wireless communication interfaces which have become available with modern microcontrollers enable the construction of such systems which can allow users to exchange information within buildings....
In this paper, we examine message prioritization in terms of both rate and reliability in the two-way relay channel using decode-forward relaying. Each source sends both a low priority message and a high priority message. We design a scheme that routes the high priority messages through the relay and direct link but the low priority message is only decoded by the destination. For fixed message priorities,...
We propose a joint list decoder and language decoder that exploits the redundancy of language- based sources during polar decoding. By judging the validity of decoded words in the decoded sequence with the help of a dictionary, the polar list decoder constantly detects erroneous paths after the decoding of every few bits. This path-pruning technique based on joint decoding has advantages over stand-alone...
The encroachment of technology grading — smaller dimensions, higher consolidation densities, and lower berth operating voltages — has come to a level that reliability of memory is put into jeopardy. Hence a novel approach is proposed to overcome this multiple cell upsets using error correction coding techniques. Recently, matrix computer code (MCs) based on senses of hamming codes have been proposed...
Real-time Audio/Video (A/V) collaboration is an application domain for which Cloud adoption is being investigated. However, the professional market generally prefers reliability over elasticity / scalability, in terms of managed delay and quality, and hence usually relies on dedicated specialized hardware and network setups, which are costly and hard to scale. This paper proposes cloud-enabled A/V...
The conventional NOR-based decoders are one ofthe fastest dynamic decoder circuits employed in microprocessors. However, they suffer from a huge amount of power dissipationresulting from the presence of short circuit paths betweenthe supply and the ground through pull-down network. Twodecoder designs with a novel selective precharge circuit have beenproposed in this paper using 32nm FinFET technology...
Research on multilingual speech recognition remains attractive yet challenging. Recent studies focus on learning shared structures under the multi-task paradigm, in particular a feature sharing structure. This approach has been found effective to improve performance on each individual language. However, this approach is only useful when the deployed system supports just one language. In a true multilingual...
Providing a high level of information reliability is one of the most important problems of digital data transmission systems synthesis for various applications. The paper suggests the theoretical foundations of communication channel model based on a code signal feature (CSF). The encoding and decoding algorithms using CSF models are proposed that allows one to increase the information reliability...
Random linear network coding simplifies routing decisions, improves throughput, and increases tolerance against packet loss. A substantial limitation, however, is delay: decoding requires as many independent linear combinations as data blocks. Hierarchical network coding purportedly solves this delay problem. It introduces layers to decode prioritized data blocks early, which may benefit video streaming...
Network coding (NC) enables us to mix two or more packets into a single coded packet at relay nodes and improve performances in wireless networks. Intra-session sliding window network coding is used at the source nodes and inter-session network coding is employed at the relay node to combine the recovered source packets of source nodes. In this paper, we investigate the performance of the network-coded...
In this paper, we investigate the limitation of existing STT-LUT designs and propose two new circuit styles of designing STT-LUTs that offer higher performance and robustness compared to the conventional STT-LUT design. The proposed styles include a Dynamic Single Rail (DSR) and a Dynamic Dual Rail (DDR) STT-LUT. The simulation results in a 16nm bulk CMOS technology shows that the proposed designs...
In this paper, bit interleaved coded modulation with the mapping of different delayed codewords onto the same signals is investigated. This scheme is referred to as delayed bit interleaved coded modulation (DBICM) and the principles of its coding and decoding are presented. Simulation results show that a coding gain of 0.7 dB and 0.5 dB can been achieved by DBICM with soft information over conventional...
The article describes an innovative bit error rate reduction technique principle and its practical implementation. The design of the technique is implemented in an FPGA and is combined with other more conventional BER reduction techniques, such as Reed-Solomon coding. Experimental results are provided. The application bit rate in function of BER for both reliable (TCP) and unreliable (UDP) mode of...
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