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This paper presents a universal BCH encoder and decoder that can support multiple error-correction capabilities. A novel encoding architecture and on-demand syndrome calculation technique is proposed to reduce both hardware complexity and power consumption. Based on the proposed methods, 32-parallel universal encoder and decoder are designed for BCH (8192+14t, 8192, t) codes, where the error-correction...
Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve optimal Energy-Perfomabilty trade-off. The proposed encoding and decoding scheme is applied to Butterfly-fat-tree (BFT) architecture. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability (0.9) at high noise...
Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardware approaches have recently been introduced for a new family of associative memories based on Sparse-Clustered Networks (SCN) that show attractive features. These architectures are suitable for implementations with low...
This paper presents a design methodology using multiplexers to implement any ternary logic function with carbon nanotube field effect transistors (CNFETs). Ternary logic is one of the promising alternatives to conventional binary logic, since it is possible to achieve simplicity and low power dissipation due to the reduced circuit such as interconnects and chip area. The paper presents a design methodology...
Motivated by the problem of designing fault-tolerant memories built out from unreliable components, this paper investigates the performance of two noisy Min-Sum-based decoders on Binary Symmetric Channels. We analyze the performance of the noisy Min-Sum decoder in terms of useful regions and target bit-error rate threshold values, derived by using “noisy” density evolution equations. We also present...
ACS (Add-Compare-Select) units are the most important block in FEC (Forward Error Correction) decoders such as Viterbi decoder and Turbo decoder. Due to the increase of performance requirement in next generation mobile communication systems such as LTE-Advanced, high speed operation of ACS units also becomes more important to achieve high throughput requirement. In this paper, we present three types...
This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port...
This work evaluates the robustness of Low-Density Parity-Check decoders against errors due to imprecise arithmetic. While the use of imprecise arithmetic is motivated by savings in energy, delay and area, it also causes errors during the decoding process. This is a new paradigm in coding theory, which traditionally assumes that an error correction decoder operates on exact hardware and errors can...
DVB-T2 defines an optional MISO processing in its transmission chain to increase the diversity of the system with linear decoding methods such as ZF and MMSE. In this paper we propose to adapt the decoding process to choose between the simple low performance ZF decoder for non-frequency selective channels and an Adaptive K-Best Sphere Decoder (AKBSD) for frequency selective channels. We propose CIR-based...
This work aims at introducing two novel packet retransmission techniques for reliable multicast in the framework of Instantly Decodable Network Coding (IDNC). These methods are suitable for order- and delay-sensitive applications, where some information is of high importance for an earlier gain at the receiver's side. We introduce hence an Unequal Error Protection (UEP) scheme, showing by simulations...
Although various universal algorithms have been proposed for Key Equation Solver(KES), the most critical part of Reed-Solomon(RS) codes, little optimization has been done for their binary sibling-binary BCH codes. This paper presents two binary versions of reformulated inverse-free Berlekamp-Massey (riBM) algorithm. The proposed algorithms halve iteration cycles and arrange variables more flexibly...
This work extends the analysis and application of a digital error correction method called Muller C-element Decoding (MCD), which has been proposed for fault masking in logic circuits comprised of unreliable elements. The proposed technique employs cascaded Muller C-elements and XOR gates to achieve efficient error-correction in the presence of internal upsets. The error-correction analysis of MCD...
The Programmable Analogue and Digital Array (PAnDA) is a novel reconfigurable architecture, which allows variability aware design and rapid prototyping of digital systems. Exploiting the configuration options of the architecture allows the post-fabrication correction and optimisation of circuits directly in hardware using bio-inspired techniques. In order to reduce the overhead of extra configuration...
What decoder is, everyone knows. The paper presents a method of n-to-2n-lines decoders design in easy way. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library Moreover, some important parameters, such area, power dissipation...
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant...
As a result of technology scaling and higher integration densities there may be variations in parameters and noise levels which will lead to larger error rates at various levels of the computations. As far as memory applications are concerned the soft errors and single event upsets are always a matter of problem. The paper mainly focuses on the design of an efficient Majority Logic Detector/Decoder...
In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives...
Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. An encoder is proposed in this paper which can be used in ternary arithmetic circuits. A ternary...
In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-VTH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer...
The Reed-Solomon (RS) codes are widely used in communication systems and data storages to recover data from possible errors that occur during transmission and from disk error respectively. This paper describes a new method for error detection in the Chien Search block of RS decoders. The main feature of this method is to introduce a factorization of the error locator polynomial, which allowed us to...
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