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The quantum computing represents a new field, which is still being researched, that may have numerous applications in the computer arithmetic, in the encryption - decryption systems, rapid search algorithms and physical systems' emulations. The hardware device that can make this type of calculations is still expensive nowadays and the number of the manufacturers is reduced. On the other hand, the...
Reversible logic has received great importance in the recent years because of its in-cogitative feature of reduction in power dissipation which is the key requirement in low power digital designs. It has wide applications in advanced computing, low power CMOS design, optical information processing, DNA computing, bio information, quantum computing and nanotechnology. In this paper a new reversible...
Spin transfer torque magnetic random access memory (STT-MRAM) has become one of the leading candidates for the next generation memory applications, thanks to its many attractive features. However STT-MRAM faces severe reliability challenges because of its intrinsic physical characteristics and the continuously scaling technology process. Thereby multi-bit error correction codes are considered indispensable...
Scaling supply voltage to near-threshold is a very effective approach in reducing the energy consumption of computer systems. However, executing below the safe operation margin of supply voltage introduces high number of persistent failures, especially in memory structures. Thus, it is essential to provide reliability schemes to tolerate these persistent failures in the memory structures. In this...
In this paper, the architecture of an SOA-based N-bit decoder, with minimum number of SOAs using Cross-Gain Modulation (XGM), is described. A 2-bit decoder is integrated under Multi-Project Wafer (MPW) photonic foundries in indium phosphide (InP) technology. Its output signals are analysed off chip and its performance is evaluated at 10 Gbps with RZ amplitude-modulated signals.
In this paper we investigate the complexity of a modified MQ arithmetic decoder architecture for error resilient JPEG2000 applications, based on the concept of ternary arithmetic decoder employing a forbidden symbol. Such ternary coding schemes have been already investigated to prove its excellent figures in terms of both PSNR and visual quality. However the complexity of the modified MQ decoder and...
This paper describes a fully-integrated 77-GHz distant-selective pseudo-random noise coded Doppler radar transceiver in a Silicon-Germanium technology. The transceiver is capable of measuring a vibration or a velocity of a target at a specified distance, which is programmable and can be configured very precisely in the transceiver, and suppressing all other targets elsewhere. It is equipped with two...
After 500-hour HTOL reliability test on memory device, off-state leakage was found in nMOSFETs of word-line decoder. According to electrical and physical failure analysis on IC and device level, we found that holes were trapped in SiN of STI edge, which lowered threshold voltage of nMOSFETs and lead to off-state leakage from drain to source. The hole-traps came from anode gate low current flow and...
This paper presents a non-binary LDPC decoder based on stochastic arithmetic. Although the previous stochastic works reduce the complexity of check node by transforming the convolution of the SPA algorithm to the finite field summation, the stochastic decoder still has a implementation bottleneck due to large storage introduced by the variable node process. Considering a balance between algorithm...
It is strongly demanded to reduce power consumption in wiring such as data bus of Complementary Metal Oxide Semiconductor (CMOS) logic circuits, especially used in mobile devices. The power consumption in CMOS is proportional to transition rate between ‘0’ and ‘1’ of each bit, and a lot of methods to reduce the transition rate have been proposed. On the other hand, in band-limited data, such as audio...
This paper presents an efficient min-sum-based decoder for high-rate low-density parity-check (LDPC) codes, where the first minimum and second minimum values are stored in registers. In order to meet a strict cost requirement imposed by NAND flash applications, we provide different upper limits for the first and second minimum values. Furthermore, we use non-uniform quantization for the second minimum...
This paper focuses on geostationary satellite scenarios and investigates the performance of several Transmission Control Protocol (TCP) variants in a novel Performance Enhancing Proxy (PEP) architecture solution, whose added value is the use of network coding beneath the transport layer. Comparison of TCP New-Reno, Vegas, Scalable, CUBIC, Hybla, and HTCP and the cases where these transport protocols...
The design of a high speed current steering DAC using 90 nm CMOS technology is presented. The resolution for this design is 10 bits, segmented into 6 thermometer encoded current cells and 4 binary weighted current cells. Thermometer encoding is used instead of binary coded decimal to reduce glitches since only one bit changes at a time. The design methodology of the sub-components such as current...
Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct a few errors in just a few nanoseconds; for example to cope with failure mechanisms that could arise in new storage physics. Fast ECCs are also desired for eXecuted-in-Place (XiP) and DRAM applications. This paper shows the key elements to implement a BCH code able to correct 2 errors in a page of 256 data bits...
Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, programmable logic devices such as FP-GAs are the implementation platform of choice due to their higher flexibility compared to ASICs and lower power...
In recent years, machine-to-machine (M2M) networks have been widely considered in wireless communication systems. Machines typically have constrained power, and their processing and communication capabilities are limited. To avoid the transmission of redundant information in order to save the transmission power, compressive sensing (CS) is a promising tool to consider. In this paper, under the two-tier...
Digital circuits are preferred over its analog counterpart with the invention of microprocessors, microcontrollers, digital signal processors and Field Programmable Gate Arrays (FPGA). Digital circuits in the form of digital arithmetic and digital logics are employed for various applications. On the other side, Support Vector Machine (SVM) is considered as a state-of-the-art tool for pattern recognition...
In this paper realization of 2:4 reversible decoder is proposed which can provide active high as well as active low outputs. The proposed decoder uses Feynman and Fredkin gates and has low quantum cost The proposed gate is fist extended to 3:8 decoder followed by an n-input decoder. The theoretical proposition is verified through SPICE simulations. A comparison with existing reversible decoders is...
The main aim of VLSI designers being low power design, this paper presents a CMOS-based new design approach for a low power adiabatic 4∶2 Priority Encoder and a 2∶4 Decoder. The proposed designs are compared with the standard adiabatic logic styles- PFAL, ECRL and 2n2n2p, revealing lesser power consumption. The simulation is carried out in NI-Multisim software at 0.5 µm CMOS technology for frequency...
Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to Bias Temperature Instability and Hot Carrier Injection. As a result, device delays increase over time reducing the Mean Time To Failure (MTTF) of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically...
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