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This paper presents a character-level sequence-to-sequence learning method, RNNembed. Specifically, we embed a Recurrent Neural Network (RNN) into an encoder-decoder framework and generate character-level sequence representation as input. The dimension of input feature space can be significantly reduced as well as avoiding the need to handle unknown or rare words in sequences. In the language model,...
In this paper, a new method for the construction of a quantum stabilizer code from circulant permutation matrices is discussed. First, we choose a finite-length vector randomly, and we can construct circulant permutation matrices from the vectors. Then, the parity-check matrix can be produce from the circulant permutation matrices. Hence, the generators of stabilizer code are determined according...
This paper proposes an area-efficient partial-sum generator (PSG) architecture for polar decoder implementation. High-throughput PSG designs mainly consist of an encoding matrix generator and a partial-sum update circuit. The matrix generator conventionally is built by cascading a series of D flip-flops and XOR gates. By decomposing the target matrix into the Kronecker product of smaller matrices,...
A 12-bit 8-4 segmented current-steering digital to analog converter (DAC) is presented in this paper. The designed DAC consumes low power compared to similar designs. The number of control signals and chip area are also decreased considerably. High performance of the proposed DAC owes to appropriate segmentation of the digital input bits and employment of a new nested Binary to Thermometer (BT) decoder...
Memory is an integral and important component in most of the digital circuits. It is basically used for storing and retrieving data in many electronic circuits. In recent days, the soft errors affecting digital circuits have become the biggest challenge for memory applications. As technology is scaling down, the effect of single error upsets (SEUs) on memories further increased the concern on their...
Channel coding for the next generation communication system needs to support higher data throughput and transmission rate. Due to the inherent parallel feature, low density parity check (LDPC) codes comply with the target. In this paper, we propose a complete channel coding scheme based on structured LDPC codes. In our design, the correlation among different parity check matrices for different code...
Reversible logic is an emerging technology with wide spread applications in the field of digital systems. The term RAM refers to memory that is accessed with an address and has latency independent of address. In semiconductor memories RAM usually refers to volatile memory read/write memory as opposed to ROM (read only memory). The 2n×2m×1 RAM has n rows and m columns, out of which one bit is selected...
Polar codes have become one of the most attractive topics in coding theory community because of their provable capacity-achieving property. Belief propagation (BP) algorithm, as one o f the popular approaches for decoding polar codes, has unique advantage of high parallelism but suffers from high computation complexity, which translates to very large silicon area and high power consumption. This paper,...
LDPC decoders on faulty hardware have received increasing attention over the last few years, mainly motivated by reliability issues in emerging nanotechnologies. As a main result, it was shown that LDPC decoders are naturally robust to hardware faults. LDPC encoders on faulty hardware have received less attention, and they are expected to be less robust to hardware faults. In this work, we propose...
RAM decoders were simulated on base the bulk CMOS 28-nm design rule. The result of a single nuclear particle impact on a MOS logical gate is a noise pulse as a single-event transient. The internal error decoder gives the main contribution to a noise sensibility of a RAM decoder. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output...
This paper is based on cyclic redundancy check based encoding scheme. High throughput and high speed hardware for Golay code encoder and decoder could be useful in digital communication system. In this paper, a new algorithm has been proposed for CRC based encoding scheme, which devoid of any linear feedback shift registers (LFSR). In addition, efficient architectures have been proposed for both Golay...
This paper focuses Two's complement multipliers with Shortest Bit-size were used without any increase in the delay of the partial product stage. This was done by reducing one row the maximum height of the partial product array generated by a radix-4 Modified Booth multiplier, this reduction may allow for a faster compression of the partial product array and regular layout. By using this method, it...
Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic design. It consists of decoder, multiplexer, memory unit, read and write units. This has been verified using VHDL. In addition to that,...
High-resolution digital-to-analog converters commonly employ segmented architecture. Its application requires thermometric decoder designing. This design process for high resolutions can become a challenge due to decoder complexity. In this paper, common design techniques of a thermometric decoder are discussed in details. The rule to form output logic functions is introduced. The formulas to calculate...
Continuous technology scaling makes NAND flash cells much denser. As a result, NAND flash is becoming more prone to various interference errors. Due to the hardware circuit design mechanisms of NAND flash, retention errors have been recognized as the most dominant errors, which affect the data reliability and flash lifetime. Furthermore, after experiencing a large number of programm/erase (P/E) cycles,...
In this paper, an Analog to Digital Converter (ADC) based on binary-search algorithm is proposed. Existing binary-search based ADC design requires 2N-1 comparators for an N-bit ADC while the proposed design requires only N comparators. This ADC uses a switching network made up of static logic gates and MOSFET switches for predicting the reference voltage for the comparators. The proof-of-concept 3-bit...
For the first time, a CO2 far-infrared laser annealing (CO2-FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-area-small-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-Al metal inter-connects. Such a far-infrared laser...
Reversibility of logic module has eminent application in low power CMOS design, quantum computing, nanotechnology and optical computing. On the other hand, configurability of PLDs (Programmable Logic Devices) reduces NRE (Nonrecurring engineering) cost and makes faster design process that offers customer a wide range of logic capacity, features, speed and voltage characteristics. In this paper, we...
The analog implementation of error control decoders is a competitive methodology compared with the digital implementation in power efficiency and throughput. In order to detect uncorrectable frames and early stop the iterative decoding of low-density parity check (LDPC) analog decoders, a probability stopping block using probabilities of satisfied checks is proposed. Simulation results show that the...
In Digital Linear Dropout (Digital LDO) implementation for System-On-Chips (SOC), the power gates operate in triode region and are distributed in bank structure. With wide dropout, the current distribution in the power gate bank turns out to be the key challenge. The proposed work presents a methodology/algorithm to distribute the current flowing through the bank of a digital LDO uniformly in a 14nm...
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