The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A low-cost low-power baseband processor for passive UHF RFID tag based on self-defined protocol is presented in this work. In order to be driven by the on-chip antenna, baseband processor employs various methods of low power technology, including GSLA (Globally Synchronous Locally Asynchronous) concept, multiple working voltages, scaling frequency of some modules, clock-gating, reuse of registers,...
We describe the benefit of using closed-loop measurements for a radio receiver paired with a counterpart transmitter. We show that real-time analysis of the soft decision output of a receiver can provide rich and relevant insight far beyond the traditional hard-decision bit error rate (BER) test statistic. We describe a Soft Decision Analyzer (SDA) implementation for closed-loop measurements on single-...
A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The algorithm uses a moving window technique adjustable to the cluster size in order to minimize the FPGA resources required for cluster identification. The window size is generic and application dependent (size/shape of clusters in the input images). A key element of this algorithm is the possibility to instantiate...
Mobile devices such as smart-phones and tablets are becoming the most important channel for delivering end-user Internet traffic especially multimedia content. One of the most popular multimedia application is video streaming. The video decoding process of this application is compute-intensive and is responsible of the consumption of a considerable part of the energy budget. Those mobile devices contain...
Turbo coding is commonly used in the current wireless standards such as 3G and 4G. However, due to the high computational requirements, its software-defined implementation is challenging. This paper proposes a static multi-issue exposed datapath processor design tailored for turbo decoding. In order to utilize the parallel processor datapath efficiently without resorting to low level assembly programming,...
Proton irradiation results, including dose and single-event effects, for two vertical-cavity surface-emitting laser (VCSEL) diodes and a matching photodiode are presented. The optical components are part of a space instrument communications link for which the bit error rate was also measured during proton beam irradiation. A high-level description of the link hardware design and associated Manchester...
A new type of low power decoding circuit for asynchronous sigma delta modulators is presented. The circuit implements a special coarse-fine time-to-digital converter to quantize the square wave produced by asynchronous sigma delta modulators, and converts the duty cycle to a digital output. The time-to-digital converter operates asynchronously by utilizing vernier delay lines. The purpose of this...
Recent work on homotopy type theory exploits an exciting new correspondence between Martin-Lof's dependent type theory and the mathematical disciplines of category theory and homotopy theory. The mathematics suggests new principles to add to type theory, while the type theory can be used in novel ways to do computer-checked proofs in a proof assistant. In this paper, we formalize a basic result in...
The proposed low-cost, scalable, synthesizable Voltage-Frequency Adjustor (VFA) design provides voltage and frequency automatic adjustments for implementing low-power systems. This design is effective in reducing power consumption from managing the supplied current and clock frequency for the structurally dynamic varying systems. The VFA supplied electrical current amount and voltage level are automatically...
Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel...
Low-density parity-check (LDPC) codes are adopted in many applications due to their Shannon-limit approaching error-correcting performance. Nevertheless, belief-propagation (BP) based decoding of these codes suffers from the error-floor problem. Recently, a new type of decoders termed finite alphabet iterative decoders (FAIDs) were introduced. The FAIDs use simple Boolean maps for variable node processing...
Non-binary low-density parity-check (NB-LDPC) codes have some advantages as opposed to their binary counterparts, but unfortunately their decoding complexity is a significant challenge. Hence, iterative hard-reliability-based majority-logic decoding (IHRB-MLGD) algorithms are attractive for NB-LDPC codes due to their low complexities. In this paper, we propose a layered improved iterative hard-reliability-based...
Low Density Parity Check (LDPC) decoders have an inherent capability of correcting the transmission errors that occur, when communicating over a hostile wireless channel. This capability allows LDPC-coded schemes to employ lower transmission energies than uncoded schemes, at the cost of introducing a significant processing energy consumption during LDPC decoding. Traditional energy-reduction techniques,...
High speed and low power Viterbi Encoder Decoder of rate ½ convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi encoder-decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it's functioning on 393.544 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the...
As the technology moves into the nano-realm, traditional single-error-correcting, double-error-detecting (SEC-DED) codes are no longer sufficient for protecting memories against transient errors due to the increased multi-bit error rate. The well known double-error-correcting BCH codes and the classical decoding method for BCH codes based on Berlekamp-Massey algorithm and Chien search cannot be directly...
Maximum a posteriori probability (MAP) decoder is an integral part of the most exciting error correcting turbo decoders. A high speed architecture for MAP decoder is an essential entity for the design of high throughput turbo decoder which is widely used in the recent wireless communication standards. In this paper, a new sliding window approach for the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm used...
In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives...
The field of Electronics and Communication Applications, especially the VLSI design, has witnessed tremendous changes on account of research and development in SoC (System-on-Chip) technology during the last four decades. The introduction and advancement of multimillion-gate chips technology with new levels of integration has been mainly responsible for these revolutionary changes. It is predicted...
In this paper, we present HCS - Heterogeneous CRAM Scrubbing - for FPGAs. By utilizing stochastic fault modeling for SEUs in CRAM, we present a quantitative estimate of system MTTF improvement through CRAM scrubbing. HCS then leverages the fact that different SEUs have unequal effects on the circuit system operation, and thus the CRAM bits can be scrubbed at different rates based on the sensitivity...
In this paper we analyze and describe the impact of processor performance parameters such as: ‘Resource Stalls, Branch Mis-predictions, Translation Lookaside Buffer (TLB) Misses and Cache Misses’ on the performance of different application domains and we analyze how this behavior varies among server processor architectures. We analyze the variant behavior of those processor performance parameters,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.