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An area-efficient and low-power low-noise amplifier with adjustable parameters for bio-potential recording applications is presented. This amplifier replaces traditional analog filters using large AC coupling capacitor with the proposed DC offset suppression block based on Differential Difference Amplifier (DDA) structure, which allows the system to obtain good high pass characterization without using...
A transimpedace amplifier (TIA) for optical links with data rate (DR) of up to 30 Gbps is presented. The design uses several bandwidth and gain enhancement techniques such as regulated common-gate, transimpedance boosting by current injection, transimpedance/transadmittance feedback and active inductor. The design is realized in a 28 nm CMOS technology. Since the circuit does not use any passive planar...
In this paper, we have proposed a 4-bit 5-GSample/s flash analog-to-digital converter (ADC) for pulse amplitude modulation (PAM) systems. In order to achieve low-power consumptions, digitalized cells for analogue amplifying are developed in the proposed ADC. Digitalized cells reduce power significantly due to using fewer devices as compared to pure analogue designs. A self-biasing circuit is used...
In this paper we present a low power, low noise CMOS micro-brain-implant which records both brain's electrical and chemical activities. We minimized the power consumption and silicon area by exploiting opamp sharing technique. This wide dynamic range (85 dB) micro device consists of a single nano-watt power amplifier for both micromolar neurotransmitter sensing and micro voltage action-potential recording...
A wideband 60 GHz on-chip triangular monopole antenna with artificial magnetic conductor (AMC) in CMOS process is presented. The AMC inserted between the lossy substrate and antenna acts as a shield to minimize the loss induced by the CMOS substrate. Both the AMC and monopole antenna are optimized to deliver a wideband operation covering all 60GHz MMW band. AMC plane in different size are studied...
A 6.25Gb/s 3-tap T/2-spaced feed-forward equaliser (FFE) is realized in 0.18μm CMOS Technology. The proposed FFE can be used to reduce the inter-symbol interference (ISI). A high frequency boost delay element using source capacitive degeneration is adopted to meet the high speed requirement. Additionally, a delay locked loop and a load calibration technique are used to overcome process variations...
This paper1 presents a linear optical receiver designed using a 28nm CMOS technology suitable for 20Gbaud/s (40Gb/s) PAM-4 modulation. The optical receiver consists of a transimpedance amplifier (gain adjustable from 40dBΩ to 56dBO) followed by a variable gain amplifier (gain adjustable from 6dB to 17dB). Capacitive peaking is used to achieve a bandwidth of ∼10GHz, thus avoiding the use of on-chip...
This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in...
This paper presents a 6th order, 700–1100 MHz, 3.6-Gb/s sampling continuous-time band-pass sigma-delta (CT BP ΣΔ) ADC realized in 65 nm CMOS technology. A high linearity transconductance-stage with Miller effect cancellation is proposed to provide above 30 dBm IIP3 over PVT corners. A 4-bit quantizer and non-return to zero (NRZ) feedback DACs are engaged in this design. The post-layout simulation...
Authors such as Thornton, Kuh, and Glasser have considered bounds on possible oscillator frequency and amplifier bandwidth based on regions of the Laplace-transform s-plane where a set of components cannot achieve real and reactive power balance. We define a “gain” that is analytic and less than unity in magnitude for values of s where power balance cannot be achieved. We then derive bounds on amplifier...
In this paper, a novel positive transformer feedback down-conversion mixer is proposed to boost conversion gain. An ultra-wideband RF input is achieved by feeding RF signal at the emitter of the switching pair. Switching devices are biased so as to minimize LO input power. Area is minimized by means of transformer coupling and shielded transmission line for RF routing. The proposed mixer is implemented...
To achieve a large bandwidth without inductor peaking, this work presents an inductor-less bandwidth-extension technique to establish Multi-Level Active Feedback (MLAF) structure that is used in a CMOS differential Trans-Impedance Amplifier (TIA). The proposed TIA consists of a trans-impedance stage, a low-pass filter, a gain stage, and an output buffer. The trans-impedance stage adopts the regulated...
This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock...
This work introduces a 94GHz duobinary keying wireless transceiver for point-to-point communications. It presents bandwidth efficiency twice as much as an OOK system and requires no carrier recovery and baseband circuitry to reduce power consumption. Designed and fabricated in 65nm CMOS, the transceiver achieves a 2.0-Gb/s data link with BER < 10−9 while consuming a total power of 265mW.
A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65nm CMOS, the prototype modulator operates at 1.28GS/s and achieves a dynamic range of 75dB, SNR of 71dB in 50MHz bandwidth, while consuming 38mW...
This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]...
A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter...
A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of...
A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm...
Thanks to technological advancements in recent decades, outstanding progress has been made in the field of neuroscience and neural engineering. Although the information processing in the brain is mostly done through neuron's electrical activities, there might be significant information in presynaptic neurochemicals. Recent studies suggest concurrent measurement of interrelated brain's electrical and...
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