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This paper presents a novel continuous time (CT) - discrete time (DT) current amplifier for electrophysiology. The architecture aims to bring together advantages from both CT and DT approaches, which are high bandwidth and low noise, respectively. The low-noise current amplifier has been implemented in 0.35 µm CMOS technology, showing input-referred noise as low as 4 fA/√Hz. It allows current recording...
In this paper, a high performance current mode logic (CML) frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). Inductive peaking structure and cascode circuit are applied in the CML frequency divider to obtain the broad-band and high frequency operation. In order to obtain a stable operation with low power, the resistor in the inductive peaking structure is replaced by the...
Folding of analog signals is one of the most efficient techniques employed in digitization of high speed signals at intermediate resolution. However, its implementation is restricted by distortion resulting from limited bandwidth at the output of the folders, interpolation at the output and comparator offset. In this paper a method to increase input signal processing capabilities and reduce the number...
This paper presents an attractive approach for bandwidth extension of a four quadrant CMOS analog multiplier. The proposed approach is based on using dynamic threshold MOS transistor (DTMOS) which is an effective technique that achieves supply voltage reduction with a simultaneous increase in the overall transconductance of the MOS transistor. The proposed multiplier can operate at very high frequencies...
A wideband, fully differential, 3-stage class-AB amplifier capable of operation at rates beyond 100 Mbps is described. Common-mode feedback is applied to increase output drive capability and reduce bias-dependent crossover distortion when operating in class-AB from a low supply voltage. Drawing 3.9mA from a nominal VDD of 1.2V in 65nm CMOS, the 0.052mm2 amplifier delivers 1.6V swing across a 50Ω load...
This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. The serializer is power-optimized by using a direct 4:1 multiplexer (MUX) at the final stage with a novel 4:1 MUX circuit design. In addition, an LC-based FFE structure that eliminates the need of multiple MUXs is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying...
A 239–281GHz imager by direct-conversion receiver is demonstrated in 65nm CMOS process with high spectrum resolution and high sensitivity for sub-THz imaging. The sub-THz imager consists of a circular-polarized substrate integrated waveguide (SIW) antenna, down-conversion mixer and power gain amplifier (PGA). The SIW antenna is compact in area of 0.17mm2 with −0.5dB gain and 32.1GHz bandwidth. The...
CMOS Technology for THz communication has been discussed in recent years, however many practical challenges remain for such data-links to be commercialized. We provide a brief overview of the wireless market and where THz may and may not fit in. Also, while the RF issues of THz links are well known, even more difficult issues in the baseband and modem still need to be addressed. This article discusses...
Users of test equipment such as oscilloscopes expect performance and accuracy beyond the level of their device under test in order to insure measurement results correspond to the DUT, not to limitations of the test equipment. This drives the use of bipolar circuitry at the front-end of high-bandwidth oscilloscopes, even if targeted at testing devices in a marketplace dominated by CMOS. Several circuit...
In this paper, a new wide-band low-voltage low-power mixer is proposed. Using a modified stacked topology in conjunction with current bleeding technique, the mixer has a power consumption of 10mw while it uses a voltage supply of 1.2 V. Parallel peaking inductors are used to increase the RF frequency and broaden the bandwidth of the mixer. The 3-dB RF frequency band of the mixer is form 7GHz to 15GHz,...
In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18μm CMOS technology...
A simple low voltage operational amplifier is introduced with an efficient class-AB output stage. Two biasing transistors are present in between common source stage. This amplifier is simulated in 0.18 µm CMOS technology. The proposed class-AB amplifier is designed to operate from ±500 mV supplies. The simulated phase margin of proposed class-AB amplifier is 87° at the load of 10 kΩ∥1 pF. The class-AB...
In this paper the Op amp circuit is implemented at low voltage, high gain, high CMRR ratio and low frequency for a biomedical application. This work evince that the composite cascade differential stage op amp operating in the weak inversion region of MOSFET, can operate at a supply voltage of 2v and provide a gain of 114db, Unity gain frequency of 6KHz and gain bandwidth of 686.98KHz (C_L=10pf) and...
We present the design and characterization of a broadband, low-noise transimpedance amplifier (TIA) with adjustable gain-peaking, implemented in 65-nm CMOS. The TIA exhibits 40-GHz bandwidth, 20-dB gain and consumes 107 mW power. An additional continuously-tunable 12-dB gain-peaking near 40 GHz is available through a simple yet effective tuning mechanism, consuming only 14% more power. The adjustable...
A Power Amplifier (PA) for wireless applications operating between 2.6 GHz and 3.4 GHz with power added efficiency (PAE) of more than 40% is presented in this paper. By varying the width of the PA transistor, the performance of the PA in terms of PAE and stability is studied. The PAE is more than 40% for the bandwidth of 800 MHz. The input matching circuit is implemented using on-chip transmission...
On-chip data processing capabilities have increased very rapidly over the last decades creating off-chip bandwidth a strong limiting factor. Limitations of this off-chip communication originate from interconnect, vias and connectors leading to reflections over chip-to-chip interconnect and leads to intersymbol interference. These variations dynamically change based on interconnect length, number of...
This paper presents the design and characterization of a high gain, high-speed differential transimpedance amplifier (TIA) to be used as the front-end interface for optical receiver applications. The TIA is realized in a standard 0.18-µm digital CMOS technology and it dissipates 25.4mW from a single 1.8 V supply. The objective of the design is to maximize the bandwidth. The main contribution of this...
This paper discusses and shows the use of Nauta operational transconductance amplifiers as integrator elements in a second-order continuous-time delta-sigma ADC. The structure is studied in order to take advantage of its potentially high bandwidth operation and simple inverter-based structure for wide output voltage range in current and future CMOS process. The second-order continuous-time delta sigma...
In this communication, one of the recently proposed active building block namely Current Differencing Current Conveyor (CDCC) has been used to design a current mode universal filters in fully differential form. The proposed universal filter has the property of independently tuneable gain, bandwidth and pole frequency. Workability of the proposed circuit has been verified using PSPICE simulation based...
The paper presents a new approach to design of current amplifiers. The amplifying cell core represents the connection of three transistors: a bias transistor and a differential pair. The bias transistor sets the distribution of currents in the differential pair. When an external current signal is applied to the core input the outputs of the differential pair provide two complementary current signals...
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