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This paper describes the design of 4.2 to 5.9 GHz CMOS power amplifier (PA) for applications in ultra-wideband (UWB) commuincations. The PA operates in the linear region over the input range of −12 dBm and delivers an output power of 6 dBm. The post layout simulations indicate the power added efficiency (PAE) is more than 35% at 5 GHz frequency and more than 20% between 4.2 GHz and 5.9 GHz. The input...
This paper deals with the susceptibility of analog integrated circuits to radio frequency interferences (RFI) and it concentrates on the effects induced by RFI on the operation of offset compensated chopped CMOS operational amplifiers. The first part of the work explains the causes of the additional output DC offset induced by input RF disturbances in chopped systems. Afterwards, the design of a chopped...
A highly linear, 3rd order, active-RC low-pass elliptic filter with Variable Gain Amplifier (VGA) is presented. The new derivative-free biquad topology for an elliptic filter could be easily extended to a higher order filter using a cascade of biquads and it will have a zero capacitive spread when used along with a VGA. It is introduced to minimize the power consumption of an active-RC filter in a...
Challenges of CMOS ADC implementations for 100 Gb/s optical communication systems and beyond are highlighted. Limitations and opportunities of architectures and circuits are discussed based on a 56–90 GS/s 8 bit ADC in 32 nm SOI CMOS.
Although CMOS active pixel sensor (APS) cameras are used as receivers for low-bandwidth visible light communications (VLC), they have typically not been used to receive high-bandwidth VLC signals. However, by selectively scanning pixels on the image sensor, the sampling rate of CMOS APS pixels can be greatly improved, enabling them to capture high-bandwidth signals while maintaining the ability to...
A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability,...
A low power CT-ΔΣ is presented which achieves 92dBA of dynamic range while consuming only 110μA from a 1.1V supply in 65nm. The ADC exploits the inherent virtual ground of the ΔΣ loop to enable low power Gm-C integrators, and a simplified excess loop-delay compensation scheme. A common-mode feedback circuit which enables low voltage operation is also presented.
Customer demands for battery powered portable electronic devices have increased. Today high data rates could be transmitted using fourth generation Long-Term Evolution (4G LTE) wireless communications standard. To increase system runtime proper envelope amplifier's architecture has to be selected. Using envelope tracking technique efficiency of the transmitter's power amplifier (PA) can be improved...
A 39MHz bandwidth (BW) CTSDM ADC realized by aggregating two 19MHz BW CTSDM ADCs with a noise-injected technique is presented. The in-band noise is improved by 4.77dB by this technique. The ADC samples at 832MS/s, achieves 72dB DR in 39MHz BW and 78dB DR in 19MHz BW. This aggregated ADC is implemented in 16-nm FinFet technology with 0.23 mm2 active area and 6.2 mW per ADC, and thereby achieves FoM...
A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.
This paper describes a low power optical receiver for discrete photodiodes. The receiver utilizes an input stage bandwidth of only 2GHz, affording high gain with low power consumption while limiting input-referred noise. The resulting ISI is eliminated and data recovered using an IIR DFE. The IIR DFE utilizes a local feedback to relax the timing criteria of the DFE loop. The 65-nm CMOS chip consumes...
This paper describes a 25-Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current boosting preamplifier with time-interleaved integrating-type optical receiver, it also circumvents CID issue with high PD bandwidth tolerance. Experimental results show that the receiver can achieve 25-Gb/s operation by integrating with a 9-GHz or 17-GHz GaAs PD. Input sensitivities...
We1 present an analog front end for a PAM-4 clock and data recovery circuit designed in 65nm CMOS. The front end consists of an arrangement of 8 interleaved master and slave sample-and-hold circuits, to be followed by an array of dynamic comparators. Each interleaved channel contains two wideband buffers with accurate bias and common-mode control circuitry to drive the sample-and-hold circuits. The...
Ultra wideband radar implementations for millimeter-/microwave operation are emerging in CMOS requiring high bandwidth. A distributed amplifier (DA) topology for use as low-noise amplifier (LNA) in nanometer CMOS, is explored in this paper. Important modifications like direct termination is beneficial both in area and gain linearity. A 5-stage amplifier provides a −3dB bandwidth of 36.5GHz and a S...
This paper presents a 1.1-V 200 MS/s pipeline ADC with 70 dB signal-to-noise-plus-distortion ratio (SNDR) and 54 mW power consumption. This performance is enabled by employing low gain amplifiers in the first two pipelined stages and digitally calibrate the inter-stage gain errors in the background using split ADC technique. To calibrate multistage in split ADC, Slope Mismatch Averaging (SMA) is used...
A fast-settling high-linearity automatic gain control (AGC) for broadband OFDM-based (Orthogonal Frequency Division Multiplexing) powerline communication (PLC) transceiver is presented in this paper. The high peak-to-average power ratio (PAPR) of OFDM signals makes conventional closed-loop AGCs impractical for the stringent settling-time constraints. A novel AGC algorithm is proposed incorporating...
In this paper, a wide range and low power multi-rate receiver for DisplayPort Version 1.3 is proposed. In order to extend the bandwidth, a high speed AC coupled interconnect receiver comprising output compensated negative impedance and positive feedback techniques is introduced. Furthermore, the automatic bit-rate tracking scheme is used for clock and data recovery (CDR) to achieve wide data rate...
RF-FPGAs and field-programmable filter arrays require tunable analog filters that can be digitally reconfigured in real-time to have several user-selected passbands and stopband notches. Such reconfigurable analog filters must operate in the microwave frequencies up to several GHz in order to meet the needs of emerging cognitive radio and reconfigurable radar front-ends. Tunable passive filters based...
This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different...
In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer...
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