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Today's car information systems (CIS) are growing into integrated cockpit systems, supporting not solely infotainment, such as navigation and AV playing/recording, but also driver assistance, such as surround view systems. Also, in-car video transfer via Ethernet is becoming widespread. Such networks connect camera modules, head unit controllers and rear-seat display units, and carry video signals...
In order to reduce the energy consumption of communication, we consider a system level model for all the components in the radio frequency (RF) part and the baseband part in low power wireless personal area networks (WPAN). In this paper, we present the power consumption model as a function of bandwidth. Using this proposed model, we discuss the total energy consumption in terms of both bandwidth...
In this paper, we aim to encourage the use of renewable power in communication systems through hybrid powering. The problem consists of optimizing the resource allocation problem using the hybrid powering from renewable and non-renewable sources. Minimizing a new defined power cost function instead of the net power consumption aims to encourage the use of the renewable power through collaboration...
System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and localized rather than evenly balanced over the chip. These two factors motivate Network-on-Chip (NoC) that...
In order to support orders of traffic explosion with sustainable energy consumption, besides conventional Spectrum Efficiency (SE), Energy Efficiency (EE) is proposed as another critical metric for the next generation mobile networks (5G). This paper proposes to evaluate the potential EE gain of 5G on the basis of EARTH Energy Efficiency Evaluation Framework (E3F). As E3F indicated, the large-scale...
Opportunistic spectrum access is a key technology for the development of novel applications with stringent QoS requirements on top of wireless sensor networks. However, the many challenges posed by opportunistic spectrum access itself are further exacerbated by the power constrained nature of wireless sensors and the QoS requirements of the applications to be supported. In this work we consider the...
In order to extend the battery life time of mobile devices, power consumption should be reduced in case of a transmission at lower data rate (DR). In optical receiver frontends the limiting or main amplifier (LA/MA) is one of the largest power consumers. This paper presents a LA/MA topology where the power can be scaled down while the gain is kept constant when lower bandwidth is required for the...
A high-speed transimpedance amplifier (TIA) with adjustable gain, high gain-bandwidth product, high energy efficiency and low noise is presented. The amplifier is designed in a 0.13µm SiGe BiCMOS technology as part of an integrated receiver front-end. A high transimpedance gain over a large bandwidth is achieved with a low stage count topology and without applying area consuming peaking inductors...
A two-stage Miller-compensated amplifier with Gm-boosting (MCG) is introduced in this paper. The design involves the conventional two-stage amplifier and a proposed wide-bandwidth scalar circuit that amplifies the output signal voltage at the first stage of the conventional two-stage amplifier. The wide-bandwidth scalar circuit has very short delay so that the non-dominant pole and right-half-plane...
It is widely accepted that a tradeoff exists between transmit power and average delay. In this paper, we consider wireless systems transmitting randomly arrived traffic over fading channels with statistical quality-of-service requirement, characterized by a delay bound and a delay bound violation probability. We study the relation between the maximal energy efficiency (EE) and the delay bound with...
A hybrid 2b-1b/cycle, two-step asynchronous SAR ADC exploiting the passive residue transfer technique is reported in this paper. The removal of the residue amplifier results in much savings in the time and power consumed for the residue transfer process. Moreover, the 2b-1b/cycle conversion scheme assisted by the asynchronous time allocation during the bit cycles further enhances the conversion speed...
Cognitive radio may discover more idle (unoccupied) spectrum by spending more power for spectrum sensing, while the transmission power can be reduced by using more spectrum (bandwidth). We analyze the tradeoff between the sensing power and transmission power in achieving a given throughput in cognitive radio networks and examine the optimum sensing bandwidth that maximizes the energy efficiency, defined...
This paper presents a low power Impulse-Radio Ultra-WideBand (IR-UWB) receiver for low range and low data rates applications. The receiver adopts a non coherent detection with duty cycling that allows very low power consumption. The receiver operates in the high band of the UWB frequency band. It has been designed for the 7.2-8.5GHz bandwidth and covers channels 8, 9, 10, and 11 of the IEEE 802.15...
Enabling the vast computational and throughput requirements of future high performance computer systems and data centers requires innovative approaches. In this paper, we will focus on the communication between computer boards. One alternative to the bottleneck presented by copper wire based cable-bound communication is the deployment of wireless links between nodes consisting of processors and memory...
This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successive-approximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most power-efficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental...
This article proposes a reconfiguration solution for CMOS frequency synthesizer with a hybrid architecture which is a combination of a Direct Digital Synthesizer (DDS) and a Phase Locked Loop (PLL). The DDS is implemented in FPGA platform functioning a reference frequency to the PLL. The PLL is designed using CMOS technology, being reconfigurable to accelerate tuning speed. Instead of employing a...
The memory subsystem (memory controller, bus, andDRAM) is becoming a bottleneck in computer system performance. Optimizing the design of the multicore memory subsystem requires good understanding of the representative workload. A common practice in designing the memory subsystem is to rely on trace simulation. However, the conventional method of relying on traditional traces faces two major challenges...
We present for the first time 32 GBd QPSK of an InP-based IQ modulator with monolithically integrated laser and co-packaged SiGe driver. Power consumption is 1.1 W, which is well within the CFP4 module overall budget of 6 W.
In this paper, we consider the delay tolerable data traffic transmission in Heterogeneous Networks (HetNet) and propose a flow-level-delay constraint small cell sleeping scheme to achieve energy saving gain. We use the flow-level model to capture the process of data transmission in micro base station (BS) which is the small cell we consider. Our scheme takes advantage of the feature of HetNet and...
The 5G vision of 10 Gb/s leads to performance and power consumption challenges in the mobile terminal receiver because 10 Gb/s requires 400 MHz bandwidth, faster baseband processing, and an increased number of component carriers and MIMO streams. The contribution of this paper is to estimate the impact from these physical layer requirements to the power consumption of main receiver components, including...
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