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Today's In-Vehicle Infotainment system requires more external memory access bandwidth (MABW) [1] especially for high definition (HD) video/audio. It demands maximum utilization for SDRAM access instead of expansion for SDRAM capacity due to limitation of chip size. An LPDDR4-3200 @32-bit SDRAM supports 12.8GB/s [2], and efficiency is limited to around 95% by SDRAM AC timing. An idea to achieve even...
Memory bandwidth is a critical issue tor a high performance and high resolution video codec. We propose a lossless compression solution to reduce memory bandwidth requirement for a multi-standard video codec. The solution is a combination of 2D-DPCM, Variable Length Coding and 4-way set-associative cache. Experimental results show that the proposed solution can reduce the memory bandwidth requirement...
Today's car information systems (CIS) are growing into integrated cockpit systems, supporting not solely infotainment, such as navigation and AV playing/recording, but also driver assistance, such as surround view systems. Also, in-car video transfer via Ethernet is becoming widespread. Such networks connect camera modules, head unit controllers and rear-seat display units, and carry video signals...
A new intra prediction scheme based on intra repetitive pixel replenishment is proposed. This scheme improves intra coding efficiency by generating adaptive texture according to an intra displacement vector that reduces prediction error for cyclic patterns and differential motion vector coding. Simulation results showed that the proposed technique improved coding efficiency by up to 2.5% BD-Rate (ΔBitrate...
This article introduces a fast hybrid architecture to perform the inverse transform for multiple standards including H.264/AVC, VC-1, MPEG-4, MPEG-2, H.263, and AVS. Both separated and common circuits are used in the hybrid architecture to get high throughput (768 Mpixel/sec for 8-point IDCT and 1536 Mpixel/sec for 4-point IDCT) while keep the area acceptable for many supported standards (56,989 logic...
A mobile digital-terrestrial-television SoC with two multi-standard video codec is integrated on a 5.3×5.4 mm2 die in 45 nm CMOS. The dual video codec with dynamic frequency selection and advanced tile-based address translation consumes 80 mW in real-time playback of full-HD MPEG-2 and SD H.264 streams from 64 bits width low-power DDR-SDRAM at 1.1V.
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