The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a small area hardware architecture for deblocking filter of HEVC is proposed. To achieve high throughput and small area, an efficient processing order based on a CTU-based pipeline is proposed. The proposed architecture is synthesized in ALTERA Cyclone V 28nm process FPGA with 28.7K gate counts. The simulation result shows that the proposed architecture achieves an area reduction of...
Securing data in machine to machine scenario is of paramount importance. With the evolving of Internet of Things (IoT) market, data should be protected from eavesdropper. Of the available cryptographic algorithms, International Data Encryption Algorithm (IDEA) is one of the most secured and highly accepted algorithm to a broad range of applications. This paper presents implementation of IDEA cryptographic...
Traditional synchronous systems relied on a global clock to maintain synchronization have incurred problems in worst-case performance and power consumption. A self-timed system that does not depend on a global clock is one of the high-caliber candidates to solve such problems. In this paper, a probabilistic self-timed system model is studied, on which task execution time is represented by a random...
Secured Hashing Algorithms are used to ensure the integrity and authenticity of data and data origin in order to achieve higher level of security. A proposed design for SHA-2 hashing functions (SHA-224, SHA-256, SHA-384, SHA-512) are implemented with fully iterative and pipelined architecture using Verilog HDL. For every hashing operation, throughput per slice plays a major role in optimized hardware...
In order to solve the problem of high-speed data collection and transmission of CCD (Charge Coupled Devices) picture element, a USB 3.0 based design of high-speed data channel for CCD system is introduced in this paper. Through analyzing the requirement of the data throughput of a specific high-resolution and high frame rate CCD system, we propose this USB3.0-based scheme. By means of testing the...
This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially OMS, which introduces a further level of impreciseness in the check-node processing unit. We show that they allow significant reduction in the memory (25% with respect...
An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation,...
Neuromorphic Engineering is the discipline of building sensory processing artificial systems inspired in the neural processing found in living beings. Biological neural brains show massive connectivity among neurons, which is not realistic to mimic using wires within silicon chips or between chips. Address-Event-Representation is a technology widely used among neuromorphic engineers to emulate such...
Multi-processor systems-on-chips are widely adopted in implementing modern streaming applications to satisfy the ever increasing computing requirements. Predictable memory hierarchies, which make memory access predictable, can better satisfy the strict timing requirements of streaming applications. However, different levels of the memory hierarchy vary in latency and capacity. Hence, the system performance...
In this paper, we present a unique methodology to implement deep IO buffers for Network-on-Chip (NoC) platform, based on a hybrid design involving conventional SRAM and emerging Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) technology. We focus on the system-level impact of probabilistic switching of STT-MRAM devices, arising when write latency of STT-MRAM is reduced through conservative...
Lightweight encryption circuits are crucial to ensure adequate information security in emerging millimeter-scale platforms for the Internet of Things, which are required to deliver moderately high throughput under stringent area and energy budgets. This requires the adoption of specialized AES accelerators, as they offer orders of magnitude energy improvements over microcontroller-based implementations...
We build upon the clean-slate, holistic approach to the design of secure protocols for wireless ad-hoc networks proposed in part one. We consider the case when the nodes are not synchronized, but instead have local clocks that are relatively affine. In addition, the network is open in that nodes can enter at arbitrary times. To account for this new behavior, we make substantial revisions to the protocol...
Solid-state drives (SSDs) are over-taking hard disk drives (HDDs) as high-volume storage in enterprise servers and data centers. However, SSDs write performance is limited due to their inability to overwrite in-place and need for garbage collection. To reduce the garbage collection (GC) overhead, a logical block address (LBA) scrambler has been proposed. However, the LBA scrambler has two issues:...
This work proposes an integrated remote terminal and bus controller: MIL-STD-1553+, implemented in 1.2 V 65-nm CMOS technology occupying 115470 μm2 of area. It incorporates a synchronous back-end and host processor interface to a true dual port memory for faster memory accesses. Employing a majority-based sampling free-running decoder at its front-end and scaled-up protocol state machines in its control...
We "naturalize" the handshake communication links of a self-timed system by assigning the capabilities of filling and draining a link and of storing its full or empty status to the link itself. This contrasts with assigning these capabilities to the joints, the modules connected by the links, as was previously done. Under naturalized communication, the differences between Micropipeline,...
This study describes a high throughput constant envelope (CE) pre-coder for Massive MIMO systems. A large number of antennas (M), in the order of 100s, serve a relatively small number of users (K) simultaneously. The stringent amplitude constraint (only phase changes) in the CE scheme is motivated by the use of highly power-efficient non-linear RF power amplifiers. We propose a scheme that computes...
This paper presents a new type of True Random Number Generator (TRNG) based on jitter and metastability implemented in the latest family of Xilinx FPGA devices. The source of randomness is the Phase-Locked Loop (PLL) that is present on such devices, which exhibits jitter due to one of the analog component in it. For extracting the random bits the design uses the same clock as the PLL's input clock...
Poor data locality in high-speed networks leads to more memory accesses of connection management, which limits the throughput performance. In view of the above problem, this paper analyzed the process of connection management and access in detail, and put forward the efficient connection management solution to improve throughput on FPGA platform. This solution takes full advantage of the structural...
Rapid improvements in integrated circuit technology over the past few decades enable increasingly large and complex Field Programmable Systems-on-Chip (FPSoC). Due to the large number of components used, the traditional bus-based interconnect scheme becomes cumbersome and restrictive. Hence, the Network-on-Chip (NoC) interconnect paradigm becomes appealing due to its many advantages such as scalability...
An efficient turbo decoder must access memory in parallel and with two different access patterns. It is shown that the problem of accessing memory both with sequential and interleaved access patterns is analogous to the graph coloring problem. The derivation proves that the obtained graph is bipartite and, therefore, only two memory banks are required in theory. For practical implementations, a system...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.