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Ultra Thin Body Devices are a way to solve technical challenges requested by advanced digital technology nodes. Combined with planar CMOS approach, they lead to the need for Ultra-Thin SOI (UTSOI) wafers. These 300 mm ultra-thin SOI layer are now available with silicon target thickness at 12 nm, controlled within a few angström range from Wafer to Wafer to Transistor level.Ultra-Thin SOI & BOX...
The feasibility of on-chip antennas for inter-tier communication on a 3D integrated circuit (IC) stack is shown for two different 3D integration processes. The on-chip antennas for inter-tier wireless interconnects are proposed to be used in conjunction with through silicon vias (TSVs) for global communication in 3D ICs. A 3D finite element method (FEM) based full wave electro-magnetic analysis of...
Today, measurement of 65nm CMOS and 130nm-based SiGe HBTs technologies demonstrate both fT (current gain cut-off frequency) and fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100nm III-V HEMT. This increase allows new millimeter wave (MMW) applications on silicon. One of the success keys is then the passive integration. In...
We report a technique which can be used to improve the accuracy of infrared (IR) surface temperature measurements made on MEMS (Micro-Electro-Mechanical-Systems) devices. The technique was used to thermally characterize a SOI (Silicon-On-Insulator) CMOS (Complementary Metal Oxide Semiconductor) MEMS thermal flow sensor. Conventional IR temperature measurements made on the sensor were shown to give...
This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive...
Low loss and high linearity antenna switch is designed and implemented using 0.18 μm silicon-on-insulator(SOI) CMOS process for GSM/WCDMA mobile phone front-ends. Body-contacts(BC) NFETs from partially depleted (PD) SOI were chosen to implement low loss and high power antenna switch. The antenna switch employs a conventional multi-stacking FET structure to distribute voltage stress toward each FETs...
In this work, the graded channel concept has been introduced into a fully-depleted 0.15 μm SOI CMOS technology through a commercial industrial fabrication process in order to improve the RF noise performance of deep submicron scale devices. The benefits of using a graded channel transistor are explicit. An improved minimum noise figure is achieved while relaxing the minimum feature size to, at least,...
A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and area-efficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a...
We propose a high voltage silicon-on-insulator (SOI) LDMOS with a Buried N-layer (BN SOI) in a self-isolation SOI high-voltage integrated circuit (HVIC). The ionized donors present in the BN enhance the interface silicon field strength from 10 V/μm of the conventional P-SOI (CP SOI) to 30 V/μm. As a result the maximum electric field in the buried oxide before the adjacent SOI breaks down (named E¡)...
RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus...
Near-perfect photonic crystal structure on 8' SOI wafer was fabricated through standard 0.13μm CMOS technology. Large scale super-collimation was demonstrated in the photonic crystal region which is coinciding with simulation result. The result represents a promising prospect of super-collimation waveguide on macroscopic optical connection.
This paper presents a low temperature (200??C) CMOS-compatible fabrication process for integrating high-temperature deposited lead zirconate titanate (PZT) on thin film monocrystalline-silicon piezoelectric actuators, onto an RF substrate, and successful demonstration of this process for fabrication of metal-contact RF-MEMS switches. The patterned PZT/silicon multi-layer stack is transfer-bonded from...
In this paper research output cascades for integrated circuits and microsystems-on-chip with silicon-on-insulator structures (SOI) of executed after traditional CMOS process and with the use of double control by connecting to the subchannels areas in SOI MOS transistors.
A single-pole double-throw novel switch device in 0.18 ??m SOI complementary metal-oxide semiconductor (CMOS) process is developed for 0.9 Ghz wireless GSM systems. The layout of the device is optimized keeping in mind the parameters of interest for the RF switch. A subcircuit model, with the standard surface potential (PSP) model as the intrinsic FET model along with the parasitic elements is built...
This paper demonstrates the effectiveness and advantages of ULP (Ultra-Low-Power) MOS diodes vs. standard implementations of a AC-DC voltage multipler in a 150nm multiple-threshold voltage SOI CMOS technology for RFID applications. Introducing a specific design methodology, we compare two 3 stages voltage multipliers, each using one of those diodes types and driving a 1.5??A load. Both architectures...
We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k...
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced...
The SIAM Medea+ project is developing circuits for 100Gbit/s optical communications for use in the next generation Ethernet backbone network. One promising bandwidth-efficient technology is sub-carrier multiplexing (SCM) where quadrature modulated (QAM) signals on different carrier frequencies are combined and subsequently encoded onto an optical carrier. This transceiver approach capitalizes on the...
The performance of on-chip passives and their application at mm-wave frequencies in two key silicon technologies are presented in this paper. Power and linear combiners designed in advanced 130 nm SiGe-BiCMOS and 65 nm CMOS-SOI are used as demonstrators. Multi-port transformer and shielded-CPW-on-SOI power combiners realize insertion loss as low as 0.5 dB and reflected port to port impedance uniformity...
A differential digital to 60 GHz quadrature mixer on a 65 nm SOI CMOS process from STMicroelectronics has been designed. Two 5 GS/s 4-bit quadrature base band signals are fully decoded and fed into an unary-weighted current DAC. The DAC output is fed to two RF Gilbert cell mixers driven by an off-chip 60 GHz LO signal. The simulated P1dB output power is -22.5 dBm for an LO power of -2 dBm at 60 GHz...
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