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Silicon-on-insulator material structure allows for very high light confinement in the silicon core due to its high refractive index. The advantages of this technology include the possibility to miniaturize devices and integrate different functions on a single chip, reduction of optical loss and power consumption and potential perspectives for low cost mass production in CMOS technology line. Together...
Large scale production of single-electron transistors (SETs) is now possible with a standard fully-depleted SOI process. Although the operating temperature is limited to approximately 10 K for now, this opens new opportunities for implementing on-chip hybrid designs combining the benefits of Coulomb blockade with regular FET-based electronics. Moreover, the continuous shrinking of CMOS devices tends...
Two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional...
This paper reports a 0.5V SOI CMOS dynamic-threshold MOS (DTMOS)/ dual-threshold (MTCMOS) circuit technique for design optimization of low-power SOC applications. Via the DTMOS/non-DTMOS technique for implementing the SOI version of the gate-level dual-threshold static power optimization methodology (GDSPOM), a 16-bit multiplier circuit has been designed, showing a performance with 30% less power...
Current architectures for the control and readout of silicon qubits often involve the use of classical CMOS electronics used at temperatures below 4K. Fully depleted silicon on insulator CMOS is a primary candidate for such electronics as they are less affected by low temperature bulk induced hysteresis and kink effects and have lower parasitic capacitances than their bulk counterparts. While MOS...
Continued increase in variability is a challenge for SRAM scaling into sub-22 nm nodes, and presents an opportunity for the introduction of alternate technologies. In this work, the performance and threshold-voltage variability of vertical SOI finFETs are compared against those of planar fully depleted (FD) SOI MOSFETs with thin buried oxide, and are presented as an alternative to planar bulk CMOS...
RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus...
A new combination of long millisecond (1-2.5 ms) flash anneal at high peak temperature(1200-1300°C) and a new absorber with low deposition temperature (<;400°C) have been developed to generate highly activated (Rs~ 500 ohm/sq), sub-20 nm abrupt (≤ 3 nm/decade) N+ and P+ junction. This new approach also provides sub-2 nm N+ and P+ junction dopant motion control with multiple long ms-flash which...
A Silicon-on-Insulator (SOI) CMOS technology on high resistivity silicon substrates is presented for the design of cellular antenna switches. The design and measurement results for an SP9T cellular antenna switch based on this technology are presented. To the best of our knowledge, this is the first demonstration of an SP9T cellular antenna switch with adequate intermodulation and harmonic distortion...
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity...
A 23 dBm class E power amplifier (PA) has been designed and simulated at 3.7 GHZ using a 130 nm CMOS-SOI technology. The PA is a single stage, single ended cascode formed by a thin oxide transistor as common source device and a laterally diffused MOS (LDMOS) transistor as common gate. Fully integrated high current inductor is used as part of the class E wave shaping network. At 3.7 GHz, the PA achieves...
A semiconductor radiation sensor requires a high-resistivity Si wafer and a high voltage to get a thick radiation sensitive region. Therefore it is difficult to fabricate both sensors and readout electronics in a planer process, and hybrid approach such as mechanical bump bonding have been used. Recently we have developed monolithic radiation detectors based on a 0.2 μm Fully-Depleted Silicon-on-Insulator...
A dual-PLL system for 45 nm SOI-CMOS processors is designed to clock a multi-protocol wireline I/O for high-speed digital communications covering a frequency range from 1 GHz up to 11.1 GHz. The two PLLs, based on a ring and LC-tank VCO, achieve .99 ps and 0.55 ps rms jitter, respectively. Circuit and architectural techniques to minimize the impact of SOI floating-body effect on phase jitter are introduced.
The POWER7TM microprocessor features a 32 kB L1 data cache with a 2R and banked-1W functionality using a 6T-SRAM cell. Read/write collision is intercepted inside the array with write-over-read priority. The array-specific power supply improves SRAM cell stability and performance while reducing the logic voltage level. The macro is fabricated in a 45nm CMOS SOI technology.
We present circuit design aspects of fully depleted extremely thin SOI (ETSOI) enabling 22 nm low-power CMOS and beyond, and demonstrate that all devices including analog, I/O, and passive devices can be fabricated in the thin silicon layer. Excellent device matching, gm/gds scaling to small gate length, good RF performance, and absence of history effect are the main features of the ETSOI technology.
An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global-bitline scheme. Finally, a data-retention-voltage sensor is developed to predict...
A 10 Gb/s optical receiver with an integrated germanium photodetector is presented. The receiver is fabricated in a silicon-photonics-enabled 0.13 μm SOI CMOS technology. The high-speed circuits consume 15 mW, achieving sensitivity of 6 μA p-p at BER = 10-12 with less than 5 ps of DJ. Photodetector dark current is 3 μA at a reverse bias of 1 V, and responsivity is 0.8 A/W.
A technique for the fabrication of planar silicon nanowires (SiNWs) on SIMOX-SOI (Separation by Implanted Oxygen-Silicon on Insulator) wafers using sidewall transfer lithography is presented, which can be used as field effect devices for biomolecular detections. Different from the existing synthesis process, this method is based on standard “top-down” semiconductor process. Aluminum sidewall is applied...
The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vt0, of MOSFETs. As a result...
A class E power amplifier (PA) has been designed and simulated for multi-radio applications in the 1.8 to 5GHz frequency band using a 130 nm CMOS-SOI technology. The PA is a single stage, single ended, self-biased cascode formed by a thin oxide transistor as common source device and a laterally diffused MOS (LDMOS) transistor as common gate. Switched fully integrated high current inductors are used...
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