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The POWER9™ Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fast and low-latency write assist schemes for single-voltage performance arrays, as well as a new methodology, the synthesized soft arrays, to enable significant...
Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz...
Noma, also known as cancrum oris, is an infectious disease that results in a loss of orofacial tissue, due to gangrene of soft and bony tissue. It is especially seen in young children in the sub-Saharan region. Among the sequelae of patients who survive noma, trismus is one of the most disabling. This retrospective research studied the long-term results of trismus release in noma patients. Thirty-six...
The POWER7TM microprocessor features a 32 kB L1 data cache with a 2R and banked-1W functionality using a 6T-SRAM cell. Read/write collision is intercepted inside the array with write-over-read priority. The array-specific power supply improves SRAM cell stability and performance while reducing the logic voltage level. The macro is fabricated in a 45nm CMOS SOI technology.
An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm partially depleted silicon on insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino...
A vector fixed point unit (FXU) is designed to speed up multi-media processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabricated using IBM 90nm CMOS SOI technology
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