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A high current driving capability charge pump circuit is proposed. By adopting the dynamic boosting circuit, the overdrive voltages of all the charge transfer switches (CTS's) in the charge pump are maintained for a large loading current. In addition, the largest voltage difference between any of the terminals of all the transistors does not exceed the supply voltage VDD, and solves the gate-oxide...
In this paper, Amplitude Shift Keying (ASK) demodulator of Radio Frequency Identification (RFID) tag module is designed as low power. RFID tag is pursued the least area, low price and low power. And the proposed ASK demodulator is designed without resistors and capacitors, differing from the existing ASK demodulator. Also, the proposed ASK demodulator is designed without envelope detector and Schmitt-trigger...
In this paper a UWB pulse generator for wireless inter and intrachip communication is introduced. The transmitter produces BPSK-modulated ultra-short Gaussian monocycle pulses of average duration 74ps. The circuit was implemented and simulated in HSPICE using IBM 90nm CMOS technology with a supply voltage of 1.2V. The transmitter performs at an input bit-rate of 10Gbps. The circuit has a low average...
This paper proposes a novel low-power fully-differential ultra-wideband (UWB) low noise amplifier (LNA) for 6-9-GHz UWB receivers in digital 90nm CMOS. The capacitive cross-coupled common-gate (CG) stage is cascaded with a cross-coupled common-source (CS) second stage to perform the wideband input impedance matching, low noise figure (NF), low power, and flat-high-wideband gain which is due to the...
A rail-to-rail CMOS continuous-time common-mode feedback (CMFB) network is introduced in this paper. The proposed scheme is based on the joint use of bulk-driven MOS transistors, which lead to high signal swing, and a partial positive feedback, which allows achieving enhanced DC gain and gain-bandwidth product. The proposed CMFB circuit is used to control the output voltage of a fully differential...
This work proposes a potentiostat circuit for multiple implantable sensor applications. Implantable sensors play a vital role in continuous in situ monitoring of biological phenomena in a real-time health care monitoring system. In the proposed work a three-electrode based electrochemical sensing system has been employed. In this system a fixed potential difference between the working and the reference...
This work presents the design and simulation of an ultra-low-power voltage-controlled oscillator (VCO) for MICS (Medical Implant Communication Service) band applications. The VCO is based on a single ended CMOS inverter ring oscillator. For the voltage control, current starving has been employed. Current for the oscillator is provided by a beta multiplier reference (BMR) which is highly insensitive...
For the first time, we demonstrate low-VT (VTlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel...
Low power and small volume are always the most important issues in the internal module of a wireless implantable neural recording system. In this paper, a BPSK demodulator base on digital-analog hybrid COSTAS Loop is presented. A digital multiplier replacing the analog multiplier is presented specially to achieve lower power consumption in the proposed circuit. The proposed BPSK demodulator features...
A high-speed, high-accuracy, low power continuous-time sigma-delta (CTSD) modulator designed by using SMIC 0.18 μm CMOS technology is presented in the paper. The fifth-order CTSD modulator comprises a fifth-order RC operational-amplifier-based loop filter and 4-bit internal quantization operating at 320 MHz. The techniques of NRZ DAC pulse shaping and half sampling period delay are adopted...
This paper presents a 2 - 13GHz low-voltage broadband down-conversion mixer with an active balun for UWB radio. The mixer with an active balun is fabricated in the 0.18 μm 1P6M standard CMOS process. The mixer with active balun consumes 15.2 mW from a 1.2 V supply. This mixer was achieved by using a folded-mixer and a peaking inductor technique. This technique can double the 3 dB bandwidth...
This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm...
The current work focuses on the design of a fully integrated single beam photoreceiver that can accept optical pulses of 850 nm wavelength at a bandwidth as high as 1 Gbps. This is highly suitable for implementation in fiber optic LANs and short haul optical interconnects. The recent advances of fiber optic communication technology with VLSI circuit design methodologies has motivated the development...
This paper proposes a 10-bit 1.25GSample/s partially-segmented D/A converter for Ultra Wide-Band communication system fabricated in a digital 0.18um 1-poly 6-metal standard CMOS technology. To achieve low power consumption and small chip area with good linearity we employ partially segmented D/A converter architecture. Also, we use deglitch circuit and common-centroid layout scheme in the current...
A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage...
A modified regulated cascode structure that incorporate a push-pull inverting amplifier and having a low output compliance voltage is used in the implementations of proposed current mirrors. P-SPICE simulations in 0.25μm CMOS technology validate the proposed current mirror structures at 1V. They offer very high output impedance about 30GΩ, consume around 200μW of power at 100μA d.c. current, and offer...
This paper presents a new micro-power precision sample-and-hold (S/H) circuit for biomedical applications. In conjunction of low-power op-amp circuit design, the switched-capacitor capacitive-reset gain circuit with capacitor-mismatch compensation technique has been used. With this combination, the S/H has features of insensitive to capacitor mismatch, offset, and finite open-loop gain of op-amp whilst...
In this work we investigate novel vertical Silicon nanowire (NW) based CMOS technology for logic applications. The performance and behaviour of two nanowire and single nanowire vertical CMOS inverter are simulated and analysed. It is seen that vertical NW MOSFET has a significant performance gain over corresponding FinFET technology. We show that nanowire based vertical CMOS offer up to 80% reduction...
In this paper a low-power low-noise amplifier for neural recording and biomedical applications is presented. The frequency band of the amplifier is tunable. It has a gain of 28.3 dB. The low and the high cut-off frequency can be adjusted from 24 mHz to 30.6 Hz and 4.5 kHz to 7.47 kHz, respectively. The circuit is designed in 0.18μm CMOS process, and it consumes only 77.8 nW at 1.8V supply voltage...
This paper proposes a high-speed and low-power bootstrapped level converter for dual-supply systems. The proposed level converter adopts a voltage bootstrapping at the gate of pull-down transistors to achieve improved driving speed and reduced contention problem. Simulation results in a 0.13-um CMOS process indicated that the proposed level converter reduces the propagation delay up to 64% and the...
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