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We present a CMOS Charge Sensitive Amplifier (CSA) specifically designed for low capacitance pixel or silicon drift detectors for high resolution X-ray spectrometry. The intrinsic noise of the CSA has been measured at different operating temperatures with a triangular shaping with peaking time from 0.8 µs to 102 µs. At room temperature, the intrinsic Equivalent Noise Charge (ENC) shows a minimum of...
A wideband resistive feedback balun low noise amplifier (LNA) is presented in this paper. The proposed LNA has a wide band gain of 22 dB in a band of 0.2–5 GHz. An improved input balun stage is used to realize a single-ended to differential conversion with optimized transconductance and amplifier open-loop gain. The wide band LNA is implemented in 65nm CMOS technology and has an area of about 0.009...
In this paper, a double-balanced Gilbert cell down-conversion mixer is demonstrated from 70-110 GHz. The wide bandwidth and high frequency are enabled by the HRL InP/Si BiCMOS process. With an fT of 300 GHz, the available 0.25 ??m InP HBTs are used in the signal path while the 90nm CMOS devices are used for biasing and gain adjustment. The fully differential circuit is implemented using two on-chip...
In this paper, we present differential Vackar voltage-controlled oscillator (VCO) implemented for the first time in CMOS technology. The Vackar VCO provides good isolation between LC tank and loss-compensating active circuit; thus, excellent frequency stability is achieved over the frequency tuning range. Simple analysis and simulations examine the transistor loading effect and amplitude stability...
This paper presents a tunable integrated electrical balanced duplexer as a compact alternative to multiple bulky SAW and BAW duplexers. A floating balancing network creates a replica of the TX signal for cancellation at the input of a single-ended LNA, thus enabling high power operation. It achieves around 50dB isolation within 1.6–2.2GHz range. The cascaded noise figure of the duplexer and LNA is...
A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate the RTN-related variation of the device drain current. The RTN parameters obtained from experimental traces are used to simulate the impact of RTN in the drain current of pMOS...
In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18μm CMOS technology...
A 2.5-GHz low power high gain and high linearity CMOS low noise amplifier (LNA) is presented. The modified derivative superposition (MDS) technique is employed to improve the linearity performance. The bulk-bias control of auxiliary transistor (AT) in MDS technique is used to extend the AT's bias control range. The current-reused topology is utilized to full-fill the low power consumption and high...
An inductorless wideband LNA is designed with low NF and high linearity. It is based on the use of both passive and active feedback with current reuse techniques to achieve the required low NF, high BW, and suitable gain. An auxiliary transistor is added to the differential implementation to achieve a high linearity. The circuit is designed in 0.13µm TSMC technology and exhibits a gain of 18.4dB over...
In this paper an RF channel select filter with improved blocker rejection is presented. The proposed filter consists of three parallel resonant tanks and two series resonant tanks all implemented with N-path switched-cap filters. Due to the inclusion of notch filters between the bandpass filters, the rejection of the filter in the vicinity of the passband is higher compared with any existing filters...
This paper reports on the world's first CMOS low noise amplifier (LNA) operating successfully on a radio telescope since October 15th, 2010. The radio telescope used in this work is the Synthesis Telescope operated by the Dominion Radio Astrophysical Observatory, NRC, and located near Penticton, BC, Canada. This paper describes the work that led to the installation of the LNA on the telescope and...
In this paper, a dual-channel interferometer-based capacitive sensor with high sensitivity is implemented in 65nm CMOS. Such architecture facilitates high throughput flow cytometry applications using intrinsic EM signatures of biological cells. To enhance SNR, injection-locked oscillator is utilized to perform phase amplification with regard to capacitance-induced frequency shift. Noise from on-chip...
A dc-80 GHz compact distributed amplifier (DA) with 15-dB small signal gain is developed in 40-nm CMOS digital process. The circuit architecture is based on the conventional DA (CDA) with gain cell of cascaded single-stage DA (CSSDA). In order to minimize the chip size, the artificial transmission-line sections of DA are implemented with microstrip-line instead of coplanar-waveguide (CPW), and the...
This paper presents a W-band LNA implemented in a 90 nm SiGe BiCMOS technology. The LNA achieves a maximum gain of 34 dB and a minimum NF of 3.5 dB at 80 GHz with greater than 25 dB gain and less than 4.5 dB NF over the full W-band. Input and output return losses are greater than 10 dB from 78–149 GHz. The circuit nominally operates from a 1.2 V supply while consuming 15.6 mW of DC power. Due to the...
This paper presents our developed two-chip wireless communication system adhering to the IEEE 802.11ad standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process. The BBIC uses an adaptive time domain equalizer rather...
This paper presents a wide-band low-power super-heterodyne RF front-end for the Medical Implant Communications Services (MICS) band. The front-end consists of a low-noise amplifier (LNA), a mixer, buffers, and passive baluns. The proposed circuits feature the techniques of current-reuse, MOSFET back-gate coupling, feedback, and current bleeding to achieve low power under acceptable noise figure (NF)...
Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of −94dBc/Hz in band and of −136dBc/Hz...
The Multi-finger layout technique has been extensively used in Nano-scale CMOS circuit design due to the increased circuit performance compared to a single finger layout. However choosing a finger width and number of fingers to optimize circuit performance is a challenging problem. In this paper the performance of a 2.4GHz single ended low noise amplifier (LNA) with a fixed total transistor width...
A 120∶1 frequency divider in 65-nm CMOS process is proposed. As a critical part of a 12.6 GHz PLL, the divider circuit divides the 12.6 GHz signal by a factor of 120 to achieve a 105 MHz reference signal. The design includes an 8∶1 analog common mode logic (CML) divider followed by a 15∶1 digital frequency divider. The measurement results show that it achieves a low phase noise of −109 dBc/Hz at 1...
In this paper a highly linear differential CMOS low noise amplifier (LNA) for ultra-wideband (UWB) applications is proposed. The proposed LNA uses a linearization technique to improve both input second- and third-order intercept points (IIP2 and IIP3), simultaneously. The linearity is improved by canceling the common-mode part of all intermodulation (IM) components from the output current. Analysis...
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