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This paper presents the design and characterization of SiGe RFICs for millimeter-wave radiometers. It is seen that SiGe technology results in high gain millimeter-wave amplifiers, high responsivity detectors and low overall 1/f noise, making it ideal for on-chip radiometers. Two example radiometer systems, one at W-band and one at D-band, are presented in detail.
This paper presents a new type of the hybrid envelope amplifier (HEA) using a switching-controlled structure for reconfigurable transmitters. The dual switching stage, controlled by an appropriate voltage with respects to the selected mode, is employed to obtain high efficiency. For verification, the proposed HEA has been fabricated using 0.35-µm CMOS technology within an area of 2.3 × 1.1 mm2 including...
A digitally-controlled switched-capacitor RF power amplifier (SCPA) that uses a dual-supply voltage, class-G architecture is implemented in 65nm CMOS. It implements signal envelope digital-to-analog conversion using switching functions controlled by digital logic to achieve superior efficiency and linearity at output power backoff. The SCPA delivers a peak (average) output power of 24.3 (16.8) dBm...
This paper presented 28 GHz single-pole-single-throw switch using a 0.18 μm CMOS process. The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST switch has insertion loss of −7.2 dB and isolation is greater than-29 dB at 24 GHz.
This paper presents a pulse-shaped power amplifier (PSPA) design for delay line based IR-UWB transmitters. By utilizing an array of CMOS transmission gates as a dynamic bias scheme, the switched PA generates desired output pulse with negligible static current. The PSPA designed in 65nm CMOS generates UWB pulses with a −10dB bandwidth of 2.7GHz and a center frequency of 5GHz and achieves reconfigurable...
This paper presents a 10b 500KS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) with input range prediction DAC switching technique for low power applications. The proposed input range prediction DAC switching technique narrows down the traditional try-and-error range of the input signal to prevent unnecessary DAC switching, and the average switching energy is...
This work presents a SAR ADC using single-capacitor pulse width to analog converter based DAC. In the proposed scheme, the single-capacitor DAC is realized by partially charging or discharging the sampling capacitor with a DC reference current. The charge and discharge time is determined by the pulse width of the control signal. As a result, a SAR ADC can be realized by using a single-capacitor, current...
Previous analytical efforts to incorporate the impact of finite switch ON-resistance into the design procedure of Class-E power amplifiers (PAs) have imposed one or both of the so-called “Class-E switching conditions”, namely zero voltage switching (ZVS) and zero derivative of voltage at switching (ZDVS). These are essential for high efficiency operation only in the absence of losses. In this work,...
This paper presents a highly linear active mixer for UMTS applications. Three source-degenerated differential pairs are used in transconductance stage to reduce the second and third-order distortion components.
Battery-powered electronics rely on integration and power efficiency for size and operational life. Switched-inductor converters play a critical role in this because most portable systems depend on dc-dc converters to supply power efficiently. Understanding the collective impact of shrinking dimensions on total power losses in a switching converter is therefore important when selecting a process technology...
A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common...
Influence of GeOx layer on resistive switching memory performance in a simple and CMOS compatible W/WOx/GeOx:WOx mixture/W structure has been investigated for the first time. All layers are confirmed by both HRTEM and XPS. This memory device has enhanced performance in terms of the resistance ratio, uniformity, and program/erase cycles as compared to W/WOx/W structure. An excellent read endurance...
This paper focuses on implementing a novel thermal switch and variable capacitance design by using commercially available CMOS MEMS process which can approach in a micro electrostatic converter system. In this system, there are two major parts. First is the variable capacitance, and the second is the thermal switch. In the variable capacitance, it implement by UMC 0.18µm one-poly seven-metal (1P7M)...
Now a day's low power Design is a essential requirement for This electronic document is a “live” template. The various components of your paper [title, text, heads, etc.] are already defined on the style hardware implementation. Technology moving into deep submicron region causes increase in leakage power. MTCMOS is promising technique for reducing leakage power but use of this technique results in...
This work presents a switched-capacitor power converter (SCPC) with a power density of 38.6mW/mm2 at 81% efficiency and 3.8mV output voltage ripple (ΔV0) in baseline 90nm CMOS. The design implements two different conversion ratios to maximize efficiency for a wide range of input voltages, and the use of 41 phases results in a very low output voltage ripple and low input current spikes.
This paper presents a high-speed CMOS OP Amp with a dynamic switching bias circuit capable of processing video signals of over 2 MHz with slight nonlinearity and low dissipated power. The OP Amp, capable of operating at 10 MHz dynamic switching rate, was designed and showed through simulations a dissipated power of 60 % of that in conventional continuous operation. A switched capacitor (SC) non-inverting...
A Delay Locked Loops (DLL) suffers from harmonic locking problem over wide-range frequency operation. Phase selection circuit plays an important in DLL. It is used not only to widen the operating frequency range and eliminating harmonic locking problems but also for fast locking mechanism. Normal phase selection circuit has the problem of generating more delayed feedback clock due to which false locking...
Envelope tracking provides the potential for achieving high efficiency in power amplifiers for next generation wireless systems with high peak-to-average ratio signals such as LTE. Envelope modulators with low cost, high efficiency and wide bandwidth are critical enablers for the widespread application of ET. This presentation reviews the development of various Si ICs for ET applications in basestation...
This work reports on the considerations for building RF switches in deeply scaled CMOS. As demonstrator single pole single throw (SPST) switches in a standard 65 nm technology are designed and measured. Goal of this design is lowest insertion loss while achieving high power handling capability, linearity, and robustness. For the novel design of switch variant Dev 1 0.8dB of insertion loss, 30dBm of...
In this paper, a new logic style named as MOS current mode logic with feedback is proposed as an alternative to conventional MOS current mode logic for implementing digital circuits operating at high frequencies. The proposed circuit style employs a positive feedback that enhances the switching speed of the circuit. The use of feedback reduces the number of transistors needed to implement the circuit...
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