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This paper proposes a novel virtual optical circuit switching (VOCS) scheme for data center networks where short flows are transmitted via optical packet switching (OPS), while long flows with reliability requirement are transmitted via VOCS. VOCS preserves the advantage of optical circuit switching (OCS) for reliable communication, while it overcomes the disadvantage of OCS in terms of low link utilization...
This paper presents a fully integrated 60 GHz power amplifier in 40nm CMOS that reaches the highest reported product of power-added efficiency and bandwidth. It is achieved through low/moderate coupling-factor transformers in the preliminary stages and a proper second harmonic termination of the output stage, such that it can operate as a class-E/F2 switched-mode PA at the saturation point. The three-stage...
This paper presents a quadrature switched-capacitor power amplifier (SCPA) that achieves similar output power and efficiency as polar/EER based digital PAs. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array in the charge domain. The SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. This counteracts losses associated with the signal combination...
This paper presents a CMOS bidirectional amplifier for time division duplexing systems. By switching supply and ground voltages of a common gate amplifier, the bias current and amplification direction can be switched between forward and backward modes. Depending on the amplification direction, CMOS switches parallel with matching inductors perform switchable matching circuits. The source and drain...
In this paper, we present a hybrid 2T gain cell based embedded DRAM with body-voltage controlled technique. The memory bit-cell is composed of a high-VTH write transistor and a standard-VTH read transistor. The negative cell-body toggle signal couples up the data ‘1’ storage level after data write. It results in an enhanced data retention time. Moreover, the proposed technique exhibits much strong...
We present an ultra-low-power Microcontroller Unit (MCU) with an embedded atom switch ROM, which performs a 0.33–1.2 V operation voltage and 46.8-µA/MHz active current (or 18.26-µW/MHz active power). The MCU is fabricated by the hybrid of Silicon-On-Thin-Buried-oxide (SOTB) CMOS and bulk CMOS [1]. The SOTB CMOS with a body-bias voltage control realizes a high drivability up to 40-MHz operation at...
In this paper, we study implementation of Boolean functions with crossbar nanoarrays where each cross point behaves as a switch. This study has two main parts "formulation" and "optimization". In the first part of formulation, we investigate Nan array based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize...
This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications...
The need for low power, area efficient and high speed comparator is pushing towards the use of clocked digital comparator which maximize speed and power efficiency. As CMOS technology scales down, various short channel effects arises which increases the leakage current due to low threshold voltage and waste some percentage of power as leakage power. This paper presents detail survey of low power techniques...
We have successfully developed the new design of MOSFET array structure with high accuracy measurement both for Ion excluding IR drop and Ioff without contamination. We propose measurement algorithm “feedback looped biasing” with kelvin probe structure and canceling method for leakage contamination due to array peripherals. This test structure is implemented in scribe line for 28nm technology and...
The market demand and efficient portable electronic equipment have pushed the industry to produce circuit designs operating at low voltage (LV) for low power (LP) consumption. Reducing the supply voltage reduces the dynamic power quadratic ally and leakage power linearly to the first order. Hence, supply voltage scaling has remained the major focus of the low power design. This has resulted in circuits...
In recent years demand of low power devices is increasing and the reason behind this is scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of transistor in system on chip (SOC) increases and this phenomenon also apply on memories that are used in SOC. Generally the number of transistors used in chip to store data is more as compared to the number of transistors used...
In this paper the analysis of DRAM logic compatible 3T cell has been shown. Due to its high density and low cost of memory, it is universally used by the advanced processor for on chip data and program memory. DRAM has transistor-capacitor cell structure, where capacitor is charged to produce 1 or 0. Memory array, which is arranged in row and column, is word line and bit line respectively. Here I...
New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized...
This paper presents the design of a novel Phase Frequency Detector (PFD) and Charge Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our proposed PFD technique can eliminate the effect of missing edge and phase ambiguity problems in conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch...
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been...
This work describes the design and implementation of an inductorless, low power, high conversion gain fully differential subharmonic down-conversion mixer for 2.4 GHz application. A complementary current-reuse technique is adapted between the transconductance stage and LO switching stage to boost the conversion gain without additional power consumption by reusing the DC current of the LO switching...
A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are...
Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this...
We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic...
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