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Near-threshold computing (NTC) is an effective technique for improving the energy efficiency of a CMOS microprocessor, but suffers from a significant performance loss and an increased sensitivity to voltage noise. MOS current-mode logic (MCML), a differential logic family, maintains a low voltage swing and a constant current, making it inherently fast and low-noise. These traits make MCML a natural...
The paper provides a deep insight to the design of an adiabatic Johnson Counter which consumes low power and delivers high performance. For achieving low power dissipation in circuits the Complementary Pass Transistor Adiabatic Logic (CPAL) is used to design the flip flops. The design of Johnson counter has been simulated and verified. The Tanner EDA tool has been used to simulate all the circuits...
An 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) is demonstrated in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16x TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL...
Power and area remain the main constraint in designing of VLSI circuits. Also, adder being one of the main components of processor design is highly researched digital module. In this paper high speed adders are designed using 130nm CMOS process and are being evaluated for their performance at lower technologies. The power dissipation, delay and area are compared for Carry select adder, ripple carry...
In this paper, we designed a 16-bit BCD adder using power gating design, dual threshold voltage (DVT) and LECTOR technique. To achieve high density, low power and high performance device scaling has been continuously done that results in increase in leakage power dissipation. At nanometers technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
Through three-dimensional numerical simulations, we investigate the use of ellipsoidal layout style on the electrical performance of a Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) switch. This gate geometry is capable to adding two new effects in the MOSFET structure named Longitudinal Corner Effect (LCE) and Parallel Connection of MOSFET with Different Channel Lengths Effect...
This paper presents design of an improved start-up circuit for a micro scale solar energy harvesting system. A wide input voltage range (270mV–1.8V) start-up circuit that can work in strong as well as weak illumination levels without causing any stress and reliability issues to the CMOS devices has been proposed. The use of native device (zero-Vth) and ultra-low power Band-gap Reference (BGR) helps...
A GPS and Miracast RFIC-on-chip antenna in 0.18 um CMOS 1p6M process is presented. The HFSS 3-D EM simulator is employed for design simulation. A printed 1.575GHz and 2.4GHz antenna has been realized by using the CMOS RFIC-on-chip. The measured VSWR is less than 2 from 1.575GHz and 2.4- to 2.483-GHz. This propose super quadric combo antenna in free space, electromagnetic coupling between super quadric...
A non-volatile programmable logic (NPL) with atom switch significantly accelerates performance of micro-controller unit. A low-power 32bit-CPU using a 65 nm-node Silicon-on-Thin-Box (SOTB) CMOS performs 1.95 DMIPS/MHz and 33 μW/MHz on 25 MHz and VDD=0.4V. When a software process in the CPU is offloaded to NPL, the 9 times faster processing speed and 3 times higher energy efficiency are realized. A...
A non-volatile programmable logic (NPL) with atom switch significantly accelerates performance of micro-controller unit. A low-power 32bit-CPU using a 65 nm-node Silicon-on-Thin-Box (SOTB) CMOS performs 1.95 DMIPS/MHz and 33 µW/MHz on 25 MHz and VDD=0.4V. When a software process in the CPU is offloaded to NPL, the 9 times faster processing speed and 3 times higher energy efficiency are realized. A...
Customer demands for battery powered portable electronic devices have increased. Today high data rates could be transmitted using fourth generation Long-Term Evolution (4G LTE) wireless communications standard. To increase system runtime proper envelope amplifier's architecture has to be selected. Using envelope tracking technique efficiency of the transmitter's power amplifier (PA) can be improved...
The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements,...
As traditional CMOS scaling reaches fundamental limits, there is an increasing interest in non-charge based beyond CMOS devices that could increase the functionality of logic chips [1]. Ferroelectric tunnel junction (FTJ) devices are attractive due to their large ON/OFF ratios, non-volatile, and low energy operation [2]. Switching has been demonstrated in the metal-ferroelectric-metal (M-F-M) FTJs...
This paper presents a hybrid design based, CMOS millimeter-wave (mm-wave) single-polar single-throw (SPST) switch. The circuit design starts from the analysis and optimization of a distributed structure, while implemented using coupled lump elements for performance improvement and area-efficient layout. Moreover, a specific bias scheme is used to further decrease insertion loss by more than 0.5 dB...
A 0.5–30GHz wideband differential CMOS T/R switch is proposed with low insertion loss (IL), high power handling capacity and high TX-RX isolation. The independent bias technique is proposed to keep the transistors in ideal on/off mode to improve IL and power handling capacity. The leakage cancellation technique is introduced to cancel leakage from TX port to RX port with two match paths. The proposed...
In this paper, loss mechanisms of monolithic high frequency Class E PAs are studied. The switching behavior is analyzed to understand the discrepancy between common design equations and optimal design values as frequency scales up. Analytical results are verified by spice simulations. In addition, a design recipe is proposed for mm-Waves PAs. The design approach is adopted to compare different technology...
This paper presents a start-up circuit based upon output voltage feedback for thermal energy harvesting. The feedback loop consisting of an output load, a boost converter core, a charge-pump-based doubler and a CMOS inverter switch to track the output voltage and generate a reset signal to kickstart the boost converter. The proposed start-up circuit shows a remarkably improved start-up time of 35μs...
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