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This paper presents a power estimate method to predict the energy efficiencies of continuous-time linear equalizers for short-haul optical communications. In order to forecast the energy efficiency over data rates, which is defined as power dissipation divided by the corresponding data rate, a reference circuit meeting some major features is established, whose energy efficiency functions as the start...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
In todays scientific scenario the need for reducing power dissipation for high end devices like Analog to Digital Converters, operational amplifiers is of utmost importance. One of the important contributors to power dissipation is leakage current. In this paper we propose a charge sharing lector comparator which significantly reduces leakage current. The circuit is primarily based on the LECTOR technique...
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary...
We discuss the modelling, implementation and characterization of antenna-coupled field-effect transistor detectors for THz frequencies. Detectors have been fabricated using a commercial 65-nm CMOS foundry process. At 4.1 THz resonance frequency and optimum operation conditions a responsivity of 86 V/W and noise-equivalent power of 113 pW/√Hz has been measured.
This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments...
This paper presents an offset calibration approach that exploits the dynamic characteristics of a comparator to achieve a wide linear tuning range by placing varactors at two different internal nodes: the drains of the input pairs (Di nodes) for high linearity, and the output nodes for wider compensation range. The comparators are placed in a 3-bit 1GS/s flash ADC that will be integrated into an 8-bit...
In Miller and current buffer compensation techniques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented...
A novel circuit for precise phase detection between two signals with the same frequency is presented. It is shown how the non-idealities in conventional phase detectors give rise to nonlinearities in the average voltage vs. phase characteristic. The proposed circuit makes use of a pair of XNOR-type phase detectors, to which signal and quadrature reference clocks are applied. A decision circuit then...
A 6-input nonvolatile lookup table (LUT) circuit is proposed using an energy-efficient single-ended logic-in-memory (LIM) structure in conjunction with a magnetic tunnel junction (MTJ) device. While the use of a conventional single-ended LIM structure makes the multi-input LUT circuit compact, a long delay due to the small difference in the MTJ resistance and a large amount of dynamic power consumption...
This paper presents a CMOS Class AB power amplifier with an on-chip 180° hybrid coupler for 4G applications. Two-stage power amplifier architecture with a combination of low voltage core transistor and high voltage I/O transistors, is designed to achieve the power gain in the 180nm standard CMOS technology. The driver stage has a power gain of 18.5dB and linear output power of 12.9dBm. The power stage...
This paper presents an on-chip common-mode cancellation circuit which increases the immunity to electromagnetic interference (EMI) of integrated CMOS operational amplifiers when EMI is injected into their inputs. The circuits have been designed in the UMC 180nm CMOS technology. Two case studies have been considered: first, the common-mode cancellation circuit has been used in a Miller amplifier and...
This paper presents a voltage-mode loser/winner-take-all circuit that has high speed and accuracy with low power consumption and which is suitable for LED driver applications. The implementation mixes analog and digital circuits in order to help in improving precision. The design is based on a hysteretic comparator and, as such, achieves a very fast response time. The circuit is implemented in the...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and recharge devices to the clock, power supply (VDD) and input signals. The simulation results for the...
A linear delay element is proposed in 0.18 µm CMOS technology with a power supply of 1.8V. The proposed delay element maintains linearity over a relatively large input voltage range of 1.2V and its delay range (sensitivity) can be tuned through a bias voltage. Its power dissipation is 50μW at a clock frequency of 1GHz and its robustness in different process corners has been shown through...
A generic ultra low-voltage (ULV) CMOS design approach is presented. By applying a floating capacitor to the gate terminal of the enhanced driving transistors, obtained by using a charge injection technique, we may change the ON and OFF currents. The delay in circuits where the enhanced transistors are utilized can be reduced significantly compared to complementary CMOS. The current level of the transistors...
High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC. The comparator...
This paper describes the design techniques of a segmented current steering (CS) digital-to-analog converter (DAC)with optimum sizing of the current sources. The DAC has been designed in 0.18 μm CMOS n-well technology provided by National Semiconductor. The 10-bit DAC is segmented as 5+5, where the 5-LSB bits are implemented in binary and the 5-MSB bits are implemented in unary architecture...
This paper shows an effective and novel implementation of the self-cascode technique in the design of a CMOS active inductor in 65nm CMOS bulk technology with a triple-well process. The current operated active inductor operates at a self-resonant frequency of 0.447 GHz at a relatively low bias current (less than 150 uA) drawn from a 1.2 V voltage supply. The design methodology of the self-cascode...
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